Abstract
The high speed potential of I.C. components can be exploited by shortening the pipeline clock period. Although there are some factors which dominate the shortening, the design of an experimental computer employs the principle of maximum time difference at the system level to determine the clock period and the integrated consideration of architecture, logic design and engineering layout to achieve a system clock period of 9.8 ns using conventional ECL chips of 2ns gate delay. The multiplier in this model, which is constructed with 0.7 ns gate delay chips, can work at a clock period of 5.5 ns.
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References
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This project is partly supported by National Natural Science Foundation of China.
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Lin, Q., Xia, P. The design and implementation of a very fast experimental pipelining computer. J. of Comput. Sci. & Technol. 3, 1–6 (1988). https://doi.org/10.1007/BF02943327
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DOI: https://doi.org/10.1007/BF02943327