Abstract
A new three-stage process for partial scan design is presented. The first two stages focus on cyclebreaking, and on limiting the maximum length of consecutive self-loops, as proposed by previous researchers. For the third stage, combinational blocks and their effects on sequential test generation are evaluated using a graphtheoretic representation designated the circuit flow graph. Costs calculated from the circuit flow graph representation are then used to select additional scan flip-flops. Sequential test generation results show that our selection of scan flip-flops is generally smaller than that reported by earlier researchers, and leads to a comparable fault coverage and smaller test generation time.
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Tai, SE., Bhattacharya, D. A three-stage partial scan design method to ease ATPG. J Electron Test 7, 95–104 (1995). https://doi.org/10.1007/BF00993317
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DOI: https://doi.org/10.1007/BF00993317