Abstract
High-temperature and flux-free bonding is important for heterogeneous integration of different chips. In this work, a Cu pillar bump was prepared by electroplating and reflow for application in the heterogeneous integration of complementary metal–oxide–semiconductor (CMOS) and GaAs chips. Cu pillars were electroplated on the CMOS chip. Then, Ni, Au and Sn were electroplated on top of the Cu pillars. During the reflow process, Au and Sn diffused into each other and formed a new Au-Sn alloy which was evenly distributed with the Au5Sn phase and the Au-Sn phase. The as-prepared Au-Sn alloy was able to be soldered without flux. The CMOS and GaAs chips were bonded together using an AFC high-precision laser bonding machine. The shear strength of the heterogeneously integrated chips was tested after bonding and aging at 150 °C. Scanning electron microscopy (SEM) was used to observe the fracture morphology. Fractures occurred partly between the Cu pillars and the CMOS chip and partly at the joint interface. When fracture occurred at the joint interface, it occurred between the Ni and the interconnection layers. The cross-sections of the joints showed that after bonding, the interconnection layer mainly generated a Au-rich phase while there was no Sn-rich phase. With the increase of aging time, Ni atoms slowly diffused into the interconnecting layer. The thickness of the compound layer containing Ni, Au and Sn increased from 300 nm after bonding to 550-600 nm after aging 1000 h, while the microstructure in the interconnecting layer was unchanged.
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Hu, Y., Zhang, Y., Bao, Z. et al. A Cu Pillar Bump Bonding Method Using Au-Sn Alloy Cap as the Interconnection Layer. J. Electron. Mater. 53, 1414–1424 (2024). https://doi.org/10.1007/s11664-023-10881-1
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DOI: https://doi.org/10.1007/s11664-023-10881-1