I/O and computation overlap on SIMD systolic arrays D. LavenierF. RaimbaultP. Frison OriginalPaper 01 April 1995 Pages: 153 - 165
Synthesis of dedicated SIMD processors M. AuguinF. BoériG. Ménez OriginalPaper 01 April 1995 Pages: 167 - 179
Parallel reduced area multipliers K'Andrea C. BickerstaffMichael J. SchulteEarl E. Swartzlander Jr. OriginalPaper 01 April 1995 Pages: 181 - 191
Digit pipelined arithmetic on fine-grain array processors Chetana NagendraRobert Michael OwensMary Jane Irwin OriginalPaper 01 April 1995 Pages: 193 - 209
Rate-optimal schedule for multi-rate DSP computations R. GovindarajanGuang R. Gao OriginalPaper 01 April 1995 Pages: 211 - 232
A low-power high performance polygon renderer for computer graphics Wee-Chiew TanTeresa H. -Y. Meng OriginalPaper 01 April 1995 Pages: 233 - 255
GENES IV: A bit-serial processing element for a multi-model neural-network accelerator Paolo IenneMarc A. Viredaz OriginalPaper 01 April 1995 Pages: 257 - 273