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A low-power high performance polygon renderer for computer graphics

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Abstract

Polygon rasterization is one of the most computational and memory intensive operations in computer graphics. In this paper, we present a low-power, real-time hardware design for this task. The system is resolution-independent by configuring different numbers of render engines in a 2-dimensional array. Using an array configuration of 16 render engines for a 512×512-pixel display, a peak performance of up to 3.4 million Gouraud-shaded polygons/sec is achievable. Total power consumption, depending on the polygon throughput, ranges between 17 mW to 133 mW at 1.5 V operation. A format for transmitting polygon information is proposed at a typical bandwidth of 4 Mbps, suitable for wireless transmission. This screen and format configurable design has potential application in portable, wireless head-mounted displays for virtual reality systems.

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Authors and Affiliations

  1. Department of Electrical Engineering, Stanford University, 94305, Stanford, CA

    Wee-Chiew Tan & Teresa H. -Y. Meng

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  1. Wee-Chiew Tan
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  2. Teresa H. -Y. Meng
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This work was supported by the Advanced Research Projects Agency (ARPA).

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Tan, WC., Meng, T.H.Y. A low-power high performance polygon renderer for computer graphics. Journal of VLSI Signal Processing 9, 233–255 (1995). https://doi.org/10.1007/BF02407087

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  • DOI: https://doi.org/10.1007/BF02407087

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