Abstract
A mechanism for overlapped I/O management operations and computation on asimd linear systolic array is presented. This mechanism is based on two synchronized controllers allowing a speed-up factor of 2 oversimd machines without overlapped facility. Code generation is achieved using the C-stolic language, specifically designed for the architectural features of overlappedsimd systolic arrays.
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References
H.T. Kung, “Why Systolic Architectures?”Computer, Vol. 15, pp. 37–46, January 1982.
M. Annaratone, E. Arnould, T. Gross, H.T. Kung, M. Lam, O. Menzilcioglu, and J.A. Webb, “The Warp Computer: Architecture, Implementation, and Performance,”IEEE Transactions on Computers, Vol. C-36, pp. 1523–1538, 1987.
S. Borkar, R. Cohn, G. Cox, S. Gleason, T. Gross, H.T. Kung, M. Lam, B. Moore, C. Peterson, J. Pieper, L. Rankind, P.S. Tseng, J. Sutton, J. Urbanski, and J. Webb, “iWarp: An Integrated Solution to High-Speed Parallel Computing,”Proceedings of Supercomputing '88, pp. 330–339, 1988.
D. Lavenier,MicMacs: un réseau systolique linéaire programmable pour le traitement des chaines de caractéres, Ph.D. thesis, Université de Rennes 1, June 1989.
D. Juvin, J.L. Basille, H. Essafi, and J.Y. Latil, Sympathi2: a 1.5d processor array for image applications,EUSIPCO Signal Processing IV: theories and application, North Holland, pp. 311–314, 1988.
Richard Paul Hughey,Programmable Systolic Arrays, Ph.D. thesis, Brown University, May 1991.
P. Frison and D. Lavenier, “Experience in the Design of Parallel Processor Arrays,”International Workshop on Algorithms and Parallel VLSI Architecture II, Elsevier Science Publishers B.V., France, pp. 233–242, 1991.
F. Raimbault and D. Lavenier, Relacs for Systolic Programming,International Conference on Application Specific Array Processors, Venice, Italy, pp. 132–135, 1993.
S. Kim, M.A. Nichols, and H.J. Siegel, “Modeling Overlapped Operation between the Control Unit and Processing Elements in an SIMD Machine,”Journal of Parallel and Distributed Computing, Vol. 12, pp. 329–342, 1992.
P. Frison, D. Lavenier, H. Leverge, and P. Quinton, “A VLSI Programmable Systolic Architecture,”International Conference on Systolic Array, Press, Killarney, Ireland, 1989.
W. Hillis and G. Steele, “Data Parallel Algorithms,”ACM, Vol. 29, pp. 1170–1183, 1986.
P. Frison, E. Gautrin, D. Lavenier, and J.L. Scharbarg, “Designing Specific Systolic Array with the API15C chip,”International Conference on Application Specific Array Processors, pp. 505–517, 1990.
F. Raimbault,Etude et réalisation d'un environnement de simulation paralléle pour les algorithmes systoliques, Ph.D. thesis, Université de Rennes 1, January 1994.
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Lavenier, D., Raimbault, F. & Frison, P. I/O and computation overlap on SIMD systolic arrays. Journal of VLSI Signal Processing 9, 153–165 (1995). https://doi.org/10.1007/BF02407082
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DOI: https://doi.org/10.1007/BF02407082