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A review of soft errors and the low α-solder bumping process in 3-D packaging technology

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Abstract

This study reviews soft errors in modern electronic assemblies, through silicon via (TSV), and low α-solder bumping techniques for 3-D microelectronic packaging. The TSV fabrication involves deep reactive ion-etching process of Si wafers to form vertical holes, which are further filled with copper and joined to solder bumps. The solder bumps in close proximity to Si die thus impose a serious threat of soft errors. These soft errors responsible for the malfunction of electronic systems have become a critical issue in miniaturized and high-density packaging, like 3-D packaging. Various low α-solder bumping techniques have been reported to minimize these errors in modern microelectronic devices. A low α-solder is one that has low levels of α-particle emission, as compared to the conventional solder. In addition, it improves the performance and reliability of the solder joints, prompting the need to adopt low α-solder for bumping in TSV packaging. Thus, this paper discusses the various aspects of TSV fabrication, functional layer deposition, Cu filling into TSV, and low α-solder bumping on TSV by solder ball reflow methods.

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Acknowledgements

This work was supported by the 2016 Research Fund of the University of Seoul.

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  1. Department of Materials Science and Engineering, University of Seoul, 90 Junnong-dong, Dongdaemun-Gu, Seoul, 130-743, Korea

    D. H. Jung, A. Sharma & J. P. Jung

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  1. D. H. Jung
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Correspondence to J. P. Jung.

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Jung, D.H., Sharma, A. & Jung, J.P. A review of soft errors and the low α-solder bumping process in 3-D packaging technology. J Mater Sci 53, 47–65 (2018). https://doi.org/10.1007/s10853-017-1421-y

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