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A 3D analytical modeling of tri-gate tunneling field-effect transistors

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Abstract

In this paper, a three-dimensional (3D) analytical solution of the electrostatic potential is derived for the tri-gate tunneling field-effect transistors (TG TFETs) based on the perimeter-weighted-sum approach. The model is derived by separating the device into a symmetric and an asymmetric double-gate (DG) TFETs and then solving the 2D Poisson’s equation for these structures. The subthreshold tunneling current expression is extracted by numerical integrating the band-to-band tunneling generation rate over the volume of the device. It is shown that the potential distributions, the electric field profile, and the tunneling current predicted by the analytical model are in close agreement with the 3D device simulation results without the need of fitting parameters. Additionally, the dependence of the tunneling current on the device parameters in terms of the gate oxide thickness, gate dielectric constant, channel length, and applied drain bias is investigated and also demonstrated its agreement with the device simulations.

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Authors and Affiliations

  1. Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, 9177948974, Iran

    Saeid Marjani & Seyed Ebrahim Hosseini

  2. Department of Electrical Engineering, Sharif University of Technology, Tehran, 1136511155, Iran

    Rahim Faez

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  1. Saeid Marjani
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  2. Seyed Ebrahim Hosseini
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  3. Rahim Faez
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Correspondence to Seyed Ebrahim Hosseini.

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Marjani, S., Hosseini, S.E. & Faez, R. A 3D analytical modeling of tri-gate tunneling field-effect transistors. J Comput Electron 15, 820–830 (2016). https://doi.org/10.1007/s10825-016-0843-0

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