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A new compact CMOS C-multiplier

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Abstract

This paper presents a new compact CMOS capacitance multiplier. The multiplier is based on using the translinear principle with MOSFETs operating in subthreshold region. The multiplication factor is controllable to meet the designer requirements. Tanner TSPICE simulator was used to confirm the functionality of the design in 0.18 µm CMOS Technology. The circuit operates from ±0.75 supply voltage. Simulation results indicate that the multiplication factor can be varied from 10 to 300. The functionality of the proposed capacitance multiplier was demonstrated by using it in designing a low pass filter and a relaxation oscillator.

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Acknowledgments

This work is a partial result of the research work funded by KFUPM, Project # IN 131066.

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Authors and Affiliations

  1. King Fahd University of Petroleum and Minerals, Dhahran, Saudi Arabia

    Munir Ahmad Al-Absi, Eyas Saleh Al-Suhaibani & Muhammad Taher Abuelma’atti

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  1. Munir Ahmad Al-Absi
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  2. Eyas Saleh Al-Suhaibani
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  3. Muhammad Taher Abuelma’atti
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Correspondence to Munir Ahmad Al-Absi.

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Al-Absi, M.A., Al-Suhaibani, E.S. & Abuelma’atti, M.T. A new compact CMOS C-multiplier. Analog Integr Circ Sig Process 90, 653–658 (2017). https://doi.org/10.1007/s10470-016-0822-1

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  • DOI: https://doi.org/10.1007/s10470-016-0822-1

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