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A novel switching scheme and area-saving architecture for SAR ADC

  • Mixed Signal Letter
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Abstract

A novel area-saving architecture and energy-efficient capacitor switching scheme for successive approximation register (SAR) analogue-to-digital converters is proposed. In the proposed architecture, the higher voltage potential side of the capacitor array removes the most-significant bit (MSB) capacitor. Furthermore the proposed technique achieves 81.25% reduction in capacitor area over the conventional SAR. Based on the third reference voltage V CM and split-MSB switching procedure, the proposed switching scheme achieves 98.53% less switching energy over the conventional architecture, while no reset power dissipation. Besides the significant energy saving, this asymmetric capacitor architecture also has a well performance in linearity simulation. Resulting from the Matlab simulation for capacitor mismatch, the maximum differential nonlinearity and maximum integral nonlinearity of the proposed scheme are 0.152LSB and 0.115LSB, respectively.

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Acknowledgments

This work was supported by the National Natural Science Foundation of China (61674118, 61504104).

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Authors and Affiliations

  1. School of Microelectronics, Xidian University, Xi’an, 710071, People’s Republic of China

    Ruixue Ding, Hongzhi Liang & Shubin Liu

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  1. Ruixue Ding
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  2. Hongzhi Liang
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  3. Shubin Liu
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Correspondence to Shubin Liu.

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Ding, R., Liang, H. & Liu, S. A novel switching scheme and area-saving architecture for SAR ADC. Analog Integr Circ Sig Process 91, 149–154 (2017). https://doi.org/10.1007/s10470-017-0924-4

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  • DOI: https://doi.org/10.1007/s10470-017-0924-4

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