Skip to main content

Advertisement

SpringerLink
Log in

Two advanced energy-back SAR ADC architectures with 99.21 and 99.37 % reduction in switching energy

  • Mixed Signal Letter
  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

This letter presents novel energy-efficient switching schemes for a successive approximation register analog-to-digital converter. The new switch method consumes no switching energy in the first three comparison cycles. The average switching energy is reduced by 99.21 and 99.37 % for the signal-independent and signal-dependent common mode voltage at the comparator, respectively. A 75 % reduction in the total capacitance over the conventional scheme is also achieved. The variation of the common mode voltage at the comparator input in the proposed architecture is 50 % less than in other low power switching schemes.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16

References

  1. Zhu, Z., Qiu, Z., Liu, M., & Ding, R. (2015). A 6-to-10-bit 0.5 V-to-0.9 V reconfigurable 2 MS/s power scalable SAR ADC in 0.18 n++ CMOS. IEEE Transactions on Circuits and Systems I: Regular Papers, 62, 689–696.

    Article  MathSciNet  Google Scholar 

  2. Zhu, Z., & Liang, Y. (2015). A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-um CMOS for medical implant devices. IEEE Transactions on Circuits and Systems I: Regular Papers, 62, 2167–2176.

    Article  Google Scholar 

  3. Bocharov, Y. I., Butuzov, V., & Simakov, A. (2015). A multichannel analog-to-digital converter of signals of silicon photomultiplier arrays. Instruments and Experimental Techniques, 58(5), 623–630.

    Article  Google Scholar 

  4. Liu, C.-C., Chang, S.-J., Huang, G.-Y., & Lin, Y.-Z. (2010). A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE Journal of Solid-State Circuits, 45, 731–740.

    Article  Google Scholar 

  5. Sanyal, A., & Sun, N. (2013). SAR ADC architecture with 98 % reduction in switching energy over conventional scheme. Electronics Letters, 49, 248–250.

    Article  Google Scholar 

  6. Xie, L., Wen, G., Liu, J., & Wang, Y. (2014). Energy-efficient hybrid capacitor switching scheme for SAR ADC. Electronics Letters, 50, 22–23.

    Article  Google Scholar 

  7. Yuan, C., & Lam, Y. (2012). Low-energy and area-efficient tri-level switching scheme for SAR ADC. Electronics Letters, 48, 482–483.

    Article  Google Scholar 

  8. Srinivasan, S., & Balsara, P. (2014). Energy-efficient sub-DAC merging scheme for variable resolution SAR ADC. Electronics Letters, 50, 1421–1423.

    Article  Google Scholar 

  9. Wei, L., Duona, L., Fengcheng, M., Jiaqi, Y., Libin, Y., Lin, H., et al. (2014). A 0.6 V 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer in 0.13 μm CMOS. Journal of Semiconductors, 35(5), 055006.

    Article  Google Scholar 

  10. Zhu, Z., Xiao, Y., & Song, X. (2013). VCM-based monotonic capacitor switching scheme for SAR ADC. Electronics Letters, 49, 327–329.

    Article  Google Scholar 

  11. Song, H., & Lee, M. (2014). Asymmetric monotonic switching scheme for energy-efficient SAR ADCs. IEICE Electronics Express, 11(12), 20140345–20140345.

    Article  Google Scholar 

  12. Anand, T., Chaturvedi, V., & Amrutur, B. (2010). Energy efficient asymmetric binary search switching technique for SAR ADC. Electronics letters, 46(22), 1487–1488.

    Article  Google Scholar 

  13. Wang, H., Zhu, Z., & Ding, R. (2015). Energy-efficient and area-efficient tri-level floating capacitor switching scheme for SAR ADC. Analog Integrated Circuits and Signal Processing, 85(2), 373–377.

    Article  Google Scholar 

  14. Wang, H., & Zhu, Z. (2015). Energy-efficient and area-efficient switching scheme based on multi-reference for SAR ADC. IEICE Electronics Express, 12(4), 20141182–20141182.

    Article  Google Scholar 

  15. Tong, X., Zhang, W., & Li, F. (2014). Low-energy and area-efficient switching scheme for SAR A/D converter. Analog Integrated Circuits and Signal Processing, 80(1), 153–157.

    Article  Google Scholar 

  16. Sanyal, A., & Sun, N. (2014). An energy-efficient low frequency-dependence switching technique for SAR ADCs. IEEE Transactions on Circuits and Systems II: Express Briefs, 61, 294–298.

    Article  Google Scholar 

  17. Tong, X., & Zhang, Y. (2015). 98.8 % Switching energy reduction in SAR ADC for bioelectronics application. Electronics Letters, 51(14), 1052–1054.

    Article  Google Scholar 

  18. Tong, X., & Ghovanloo, M. (2015). Energy-efficient switching scheme in SAR ADC for biomedical electronics. Electronics Letters, 51(9), 676–678.

    Article  Google Scholar 

  19. Liang, Y., Zhu, Z., & Ding, R. (2015). SAR ADC architecture with 98.8 % reduction in switching energy over conventional scheme. Analog Integrated Circuits and Signal Processing, 84(1), 89–96.

    Article  Google Scholar 

  20. Huang, G.-Y., Chang, S.-J., Liu, C.-C., & Lin, Y.-Z. (2013). 10-bit 30-MS/s SAR ADC using a switchback switching method. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21, 584–588.

    Article  Google Scholar 

  21. Ding, Z., Bai, W., & Zhu, Z. (2016). Trade-off between energy and linearity switching scheme for SAR ADC. Analog Integrated Circuits and Signal Processing, 86(1), 121–125.

    Article  Google Scholar 

  22. Lin, M.-H., He, Y.-T., Hsiao, V.-H., Chang, R.-G., & Lee, S.-Y. (2013). Common-centroid capacitor layout generation considering device matching and parasitic minimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32, 991–1002.

    Article  Google Scholar 

  23. Bocharov, Y., & Butuzov, V. (2015). A low-power ASIC containing 10 analog-to-digital converters and buffer memory. In 2015 International Siberian conference on control and communications (SIBCON) (pp. 1–3).

  24. Anderson, T. (1972). Optimum control logic for successive approximation analog-to-digital converters. Deep Space Network Progress Report, 13, 168–176.

    Google Scholar 

Download references

Acknowledgments

This work was supported by the Creative Unit I-See, University of Bremen (Exzellenzinitiative des Bundes und der Länder).

Author information

Authors and Affiliations

  1. Institute of Electrodynamics and Microelectronics (ITEM), University of Bremen, Otto-Hahn Allee 1, 28359, Bremen, Germany

    Dmitry Osipov & Steffen Paul

Authors
  1. Dmitry Osipov
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Steffen Paul
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Dmitry Osipov.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Osipov, D., Paul, S. Two advanced energy-back SAR ADC architectures with 99.21 and 99.37 % reduction in switching energy. Analog Integr Circ Sig Process 87, 81–91 (2016). https://doi.org/10.1007/s10470-016-0707-3

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-016-0707-3

Keywords

Search

Navigation