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Trade-off between energy and linearity switching scheme for SAR ADC

  • Mixed Signal Letter
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Abstract

A high linearity energy-efficient switching scheme for successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. Monotonic switching scheme and split-capacitor technique are combined. This scheme has no reset energy consumption, and achieves purely 98.05 % less switching energy and 75 % reduction of the total capacitance over the conventional architecture. Moreover, the proposed scheme also improves the linearity of SAR ADC. The differential nonlinearity and integral nonlinearity of the proposed scheme are 0.116LSB and 0.083LSB, respectively. The proposed scheme achieves a well trade-off between energy and linearity.

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References

  1. Zhu, Z., Xiao, Y., & Song, X. (2013). VCM-based monotonic capacitor switching scheme for SAR ADC. Electronics Letters, 49(5), 327–329.

    Article  Google Scholar 

  2. Sanyal, A., & Sun, N. (2013). SAR ADC with 98% reduction in switching energy over conventional scheme. Electronics Letters, 49(4), 248–250.

    Article  Google Scholar 

  3. Xie, L., Wen, G., Liu, J., & Wang, Y. (2014). Energy-efficient hybrid capacitor switching scheme for SAR ADC. Electronics Letters, 50(1), 22–23.

    Article  Google Scholar 

  4. Ni, Y., Liu, L., & Xu, S. (2015). Mixed capacitor switching scheme for SAR ADC with highest switching energy efficiency. Electronics Letters, 51(6), 466–467.

    Article  Google Scholar 

  5. Arian, A., Saberi, M., Hosseini-Khayat, S., et al. (2012). A 10-bit 50-MS/s redundant SAR ADC with split capacitive-array ADC. Analog Integrated Circuits and Signal Processing, 71(3), 583–589.

    Article  Google Scholar 

  6. Hu, W., Lie, D.Y.C., & Liu, Y. (2012) An 8-bit single-ended ultra-low-power SAR ADC with a novel DAC switching method. In Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), IEEE (pp. 2349–2352).

  7. Zhu, Z., Xiao, Y., Wang, W., et al. (2013). A 0.6 V 100 KS/s 8–10 b resolution configurable SAR ADC in 0.18 μm CMOS. Analog Integrated Circuits and Signal Processing, 75(2), 335–342.

    Article  MathSciNet  Google Scholar 

  8. Lin, J., & Hsieh, C. (2015). A 0.3 V 10-bit 1.17 f SAR ADC with merge and split switching in 90 nm CMOS. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(1), 70–79.

    Article  Google Scholar 

  9. Xie, L., Su, J., Liu, J., & Wen, G. (2015). Energy-efficient capacitor-splitting DAC scheme with high accuracy for SAR ADCs. Electronics Letters, 51(6), 460–462.

    Article  Google Scholar 

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Acknowledgments

This work was supported by the National Natural Science Foundation of China (61234002, 61322405, 61306044 and 61376033), the National High-tech Program of China (2013AA014103)

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Correspondence to Zhangming Zhu.

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Ding, Z., Bai, W. & Zhu, Z. Trade-off between energy and linearity switching scheme for SAR ADC. Analog Integr Circ Sig Process 86, 121–125 (2016). https://doi.org/10.1007/s10470-015-0651-7

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  • DOI: https://doi.org/10.1007/s10470-015-0651-7

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