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Design Automation for Timing-Driven Layout Synthesis

  • Book
  • © 1993

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Authors:
  1. Sachin S. Sapatnekar

    1. University of Illinois, Urbana-Champaign, USA

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    You can also search for this author in PubMed   Google Scholar

  2. Sung-Mo Kang

    1. University of Illinois, Urbana-Champaign, USA

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    You can also search for this author in PubMed   Google Scholar

Part of the book series: The Springer International Series in Engineering and Computer Science (SECS, volume 198)

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Table of contents (6 chapters)

  1. Front Matter

    Pages i-xxi
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  2. Introduction

    • Sachin S. Sapatnekar, Sung-Mo Kang
    Pages 1-12

  3. Delay Estimation

    • Sachin S. Sapatnekar, Sung-Mo Kang
    Pages 13-79

  4. Transistor Sizing Algorithms: Existing Approaches

    • Sachin S. Sapatnekar, Sung-Mo Kang
    Pages 81-111

  5. A Convex Programming Approach to Transistor Sizing

    • Sachin S. Sapatnekar, Sung-Mo Kang
    Pages 113-140

  6. Global Routing Using Zero-one Integer Linear Programming

    • Sachin S. Sapatnekar, Sung-Mo Kang
    Pages 141-189

  7. Timing-driven CMOS Layout Synthesis

    • Sachin S. Sapatnekar, Sung-Mo Kang
    Pages 191-245

  8. Back Matter

    Pages 247-269
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Keywords

About this book

Moore's law [Noy77], which predicted that the number of devices in­ tegrated on a chip would be doubled every two years, was accurate for a number of years. Only recently has the level of integration be­ gun to slow down somewhat due to the physical limits of integration technology. Advances in silicon technology have allowed Ie design­ ers to integrate more than a few million transistors on a chip; even a whole system of moderate complexity can now be implemented on a single chip. To keep pace with the increasing complexity in very large scale integrated (VLSI) circuits, the productivity of chip designers would have to increase at the same rate as the level of integration. Without such an increase in productivity, the design of complex systems might not be achievable within a reasonable time-frame. The rapidly increasing complexity of VLSI circuits has made de- 1 2 INTRODUCTION sign automation an absolute necessity, since the required increase in productivity can only be accomplished with the use of sophisticated design tools. Such tools also enable designers to perform trade-off analyses of different logic implementations and to make well-informed design decisions.

Authors and Affiliations

  • University of Illinois, Urbana-Champaign, USA

    Sachin S. Sapatnekar, Sung-Mo Kang

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