Abstract
Finding the delay of a digital circuit accurately is an important part of the design and verification process. Various levels of simulation can be used, depending on the accuracy desired, and the amount of CPU time that is affordable.
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© 1993 Springer Science+Business Media New York
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Sapatnekar, S.S., Kang, SM. (1993). Delay Estimation. In: Design Automation for Timing-Driven Layout Synthesis. The Springer International Series in Engineering and Computer Science, vol 198. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3178-4_2
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DOI: https://doi.org/10.1007/978-1-4615-3178-4_2
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6393-4
Online ISBN: 978-1-4615-3178-4
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