A low-overhead scheme for testing a bit-level finite ring systolic array G. A. JullienS. BandyopadhyayM. Taheri OriginalPaper 01 November 1990 Pages: 131 - 137
Bubbles can make self-timed pipelines fast Mark R. GreenstreetKenneth Steiglitz OriginalPaper 01 November 1990 Pages: 139 - 148
A bit-level systolic architecture for implementing a VQ tree search M. YanJ. V. McCanny OriginalPaper 01 November 1990 Pages: 149 - 158
CSP-based object-oriented description and simulation of a reconfigurable adaptive beamforming architecture using the OODRA workbench Thomas L. WernimontDavid K. HwangW. Kent Fuchs OriginalPaper 01 November 1990 Pages: 159 - 172
Fault diagnosis in reconfigurable VLSI and WSI processor arrays Sy-Yen KuoKuochen Wang OriginalPaper 01 November 1990 Pages: 173 - 187