Abstract
A bit-level systolic array system for performing a binary tree Vector Quantization codebook search is described. This consists of a linear chain of regular VLSI building blocks and exhibits data rates suitable for a wide range of real-time applications. A technique is described which reduces the computation required at each node in the binary tree to that of a single inner product operation. This method applies to all the common distortion measures (including the Euclidean distance, the Weighted Euclidean distance and the Itakura-Saito distortion measure) and significantly reduces the hardware required to implement the tree search system.
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Yan, M., McCanny, J.V. A bit-level systolic architecture for implementing a VQ tree search. J VLSI Sign Process Syst Sign Image Video Technol 2, 149–158 (1990). https://doi.org/10.1007/BF00935212
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DOI: https://doi.org/10.1007/BF00935212