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Fault diagnosis in reconfigurable VLSI and WSI processor arrays

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Abstract

A systematic efficient fault diagnosis method for reconfigurable VLSI/WSI array architectures is presented. The basic idea is to utilize the output data path independence among a subset of processing elements (PEs) based on the topology of the array under test. The “divide and conquer” technique is applied to reduce the complexity of test application and enhance the controllability and observability of a processor array. The array under test is divided into nonoverlapping diagnosis blocks. Those PEs in the same diagnosis block can be diagnosed concurrently. The problem of finding diagnosis blocks is shown equivalent to a generalizedEight Queens problem. Three types of PEs and one type of switches, which are designed to be easily testable and reconfigurable, are used to show how to apply this approach. The main contribution of this paper is an efficient switch and link testing procedure, and a novel PE fault diagnosis approach which can speed up the testing by at leastO(⋎V⋎1/2) for the processor arrays considered in this paper, where ⋎V⋎ is the number of PEs. The significance of our approach is the ability to detect as well as to locate multiple PE, switch, and link faults with little or no hardware overhead.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Arizona, 85721, Tucson, AZ

    Sy-Yen Kuo & Kuochen Wang

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  1. Sy-Yen Kuo
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  2. Kuochen Wang
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Kuo, SY., Wang, K. Fault diagnosis in reconfigurable VLSI and WSI processor arrays. J VLSI Sign Process Syst Sign Image Video Technol 2, 173–187 (1990). https://doi.org/10.1007/BF00935214

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  • DOI: https://doi.org/10.1007/BF00935214

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