Guest Editorial: Reconfigurable Signal Processing Systems Wayne BurlesonNaresh Shanbhag Editorial Introduction 01 May 2001 Pages: 5 - 6
Reconfigurable Computing for Digital Signal Processing: A Survey Russell TessierWayne Burleson OriginalPaper 01 May 2001 Pages: 7 - 27
Designing Run-Time Reconfigurable Systems with JHDL Peter BellowsBrad Hutchings OriginalPaper 01 May 2001 Pages: 29 - 45
Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System Marlene WanHui ZhangJan Rabaey OriginalPaper 01 May 2001 Pages: 47 - 61
Application of Reconfigurable Computing to a High Performance Front-End Radar Signal Processor David R. MartinezTyler J. MoellerKen Teitelbaum OriginalPaper 01 May 2001 Pages: 63 - 83
Quantitative Analysis of FPGA-based Database Searching N. ShiraziD. BenyaminS. Guo OriginalPaper 01 May 2001 Pages: 85 - 96
Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead J.P. HeronR. WoodsR.H. Turner OriginalPaper 01 May 2001 Pages: 97 - 113
Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic Uwe Meyer-BäseAntonio GarcíaFred Taylor OriginalPaper 01 May 2001 Pages: 115 - 128
A FPGA-based Library for On-Line Signal Processing Dannie LauAaron SchneiderJohn Villasenor OriginalPaper 01 May 2001 Pages: 129 - 143