Abstract
Run-time reconfigurable (RTR) systems are FPGA-based systems that reconfigure FPGAs during execution to alter hardware organization and composition to meet the varying needs of applications as they execute. These systems are difficult to describe with conventional tools (schematic capture, VHDL synthesis, etc.) because most tools assume that the underlying hardware organization is static. JHDL is a Java-based design environment capable of describing, netlisting, simulating and executing complex, dynamic RTR systems. Using conventional Java syntax, users describe hardware structures as objects; as these hardware-object constructors are invoked, JHDL automatically configures hardware circuits onto FPGA hardware, thus directly supporting the dynamic nature of RTR systems with standard language constructs. JHDL also supports codesign of the software and hardware parts of the system; in other words, the entire application can be described in a single piece of Java code that can be co-simulated/co-executed with the FPGA hardware. To date, RTR design with JHDL has focused on the development of automated target recognition (ATR) systems, and working systems described in JHDL have been demonstrated.
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References
P. Bellows and B. Hutchings, “Jhdl—An hdl for Reconfigurable Systems, ” in Proceedings of IEEE Workshop in FPGAs for Custom Computing Machines, J. Arnold and K.L. Pocek (Eds.), Napa, CA, April 1998, pp. 175–184.
P. Bellows, J. Hawkins, S. Hemmert, and B. Hutchings, “A Cad Suite for High-Performance FPGA Design, ” in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, J.M. Arnold and K.L. Pocek(Eds.), Napa, CA, April 1999.
J. Vuillemin, P. Bertin, D. Roncin, M. Shand, H. Touati, and P. Boucard, “Programmable Active Memories: Reconfigurable Systems Come of Age, ” IEEE Transactions on VLSI Systems, vol. 4, no. 1, 1996, pp. 56–69.
L. Moll and M. Shand, “Systems Performance Measurement on PCI Pamette, ” in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, J. Arnold and K.L. Pocek (Eds.), Napa, CA, April 1997, pp. 125–133.
C. Iseli and E. Sanchez, “Spyder: A Reconfigurable VLIW Processor Using FPGAs, ” in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, D.A. Buell and K.L. Pocek (Eds.), Napa, CA, April 1993, pp. 17–24.
S. Gehring and S. Ludwig, “The Trianus System and Its Appli-cation to Custom Computing, ” in Field-Programmable Logic: Smart Applications; New Paradigms; and Compliers. 6th In-ternational Workshop on Field-Programmable Logic and Applications, R.W. Hartenstein and M. Glesner (Eds.), Darmstadt, Germany: Springer-Verlag, 1996, pp. 176–184.
W. Luk, N. Shirazi, and P.Y.K. Cheung, “Compilation Tools for Run-Time Reconfigurable Design, ” in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, J.M. Arnold and K.L. Pocek (Eds.), Napa, CA, April 1997, pp. 56–65.
J. Burns, A. Donlin, J. Hogg, S. Singh, and M de Wit, “A Dy-namic Reconfiguration Run-Time System, ” in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, J. Arnold and K.L. Pocek (Eds.), Napa, CA, April 1997, pp. 66–75.
M. Gokhale and E. Gomersoll, “High Level Compilation for Fine Grained FPGAs, ” in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, J.M. Arnold and K.L. Pocek (Eds.), Napa, CA, April 1997, pp. 165–173.
P. Lysaght and J. Stockwood, “A Simulation Tool for Dynami-cally Reconfigurable Field Programmable Gate Arrays, ” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4, no. 3, 1996, pp. 381–390.
J. Villasenor, B. Schoner, K. Chia, and C. Zapata, “Configurable Computing Solutions for Automatic Target Recognition, ” in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, J. Arnold and K.L. Pocek (Eds.), Napa, CA, April 1996, pp. 70–79.
M. Rencher, “A Comparison of FPGA Platforms Through SAR/ATR Algorithm Implementation, ” Master's thesis, Department of Electrical and Computer Engineering, Brigham Young University, Provo, Utah, 1996.
M. Rencher and B. Hutchings, “Automated Target Recognition on Splash 2, ” in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, J. Arnold and K.L. Pocek (Eds.), Napa, CA, April 1997, pp. 192–200.
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Bellows, P., Hutchings, B. Designing Run-Time Reconfigurable Systems with JHDL. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 28, 29–45 (2001). https://doi.org/10.1023/A:1008107104782
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DOI: https://doi.org/10.1023/A:1008107104782