Low-Cost Testing of 5 GHz Low Noise Amplifiers Using New RF BIST Circuit Jee-Youl RyuBruce C. Kim Analog and RF Design Pages: 571 - 581
Fault Detection in Switched Current Circuits Using Built-in Transient Current Sensors Y. LechugaR. MozuelosS. Bracho Analog and RF Design Pages: 583 - 598
Multiple-Constraint Driven System-on-Chip Test Time Optimization Julien PougetErik LarssonZebo Peng Test Time Reduction Pages: 599 - 611
Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees H. YotsuyanagiT. KuchiiK. Kinoshita Test Time Reduction Pages: 613 - 620
A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices Baosheng WangAndy KuoSassan Tabatabaei Interconnect Testing Pages: 621 - 630
The Coupling Model for Function and Delay Faults Joonhwan YiJohn P. Hayes Coupling Fault Model Pages: 631 - 649
