Journal of Electronic Testing

, Volume 21, Issue 6, pp 651–658 | Cite as

Abort-on-Fail Based Test Scheduling

JETTA Letter

Abstract

The long and increasing test application time for modular core-based system-on-chips is a major problem, and many approaches have been developed to deal with the problem. Different from previous approaches, where it is assumed that all tests will be performed until completion, we consider the cases where the test process is terminated as soon as a defect is detected. Such abort-on-fail testing is common practice in production test of chips. We define a model to compute the expected test time for a given test schedule in an abort-on-fail environment. We have implemented three scheduling techniques and the experimental results show a significant test time reduction (up to 90%) when making use of an efficient test scheduling technique that takes defect probabilities into account.

Keywords

SoC testing test scheduling abort-on-fail defect probability 

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Copyright information

© Springer Science + Business Media, Inc. 2005

Authors and Affiliations

  1. 1.Embedded Systems Laboratory, Department of Computer ScienceLinköpings UniversitetSweden

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