Test Generation for Crosstalk-Induced Faults: Framework and Computational Results Wei-Yu ChenSandeep K. GuptaMelvin A. Breuer OriginalPaper Pages: 17 - 28
Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface Yiorgos MakrisJamison CollinsAlex Orailoğlu OriginalPaper Pages: 29 - 42
An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment Wei-Lun WangKuen-Jong Lee OriginalPaper Pages: 43 - 53
Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption Michiko InoueEmil GizdarskiHideo Fujiwara OriginalPaper Pages: 55 - 62
State and Fault Information for Compaction-Based Test Generation Ashish GianiShuo ShengVishwani D. Agrawal OriginalPaper Pages: 63 - 72
TA-PSV—Timing Analysis for Partially Specified Vectors Liang-Chi ChenSandeep K. GuptaMelvin A. Breuer OriginalPaper Pages: 73 - 88
Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing Chih-Wen LuChung Len LeeJwu-E Chen OriginalPaper Pages: 89 - 97