Test Cycle Count Reduction in a Parallel Scan BIST Environment Bechir AyariPrab Varma OriginalPaper Pages: 409 - 418
LFSR-Based Deterministic TPG for Two-Pattern Testing Xiaowei LiPaul Y.S. CheungHideo Fujiwara OriginalPaper Pages: 419 - 426
BIST TPG for Combinational Cluster Interconnect Testing at Board Level Chen-Huan ChiangSandeep K. Gupta OriginalPaper Pages: 427 - 442
Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits Yoshinobu HigamiYuzo TakamatsuKozo Kinoshita OriginalPaper Pages: 443 - 451
IDDQ Testing of Submicron CMOS—by Cooling? M. RenczV. SzékelyB. Courtois OriginalPaper Pages: 453 - 461
False-Path Removal Using Delay Fault Simulation Marwan A. GharaybehVishwani D. AgrawalCarlos G. Parodi OriginalPaper Pages: 463 - 476
Reduction of Number of Paths to be Tested in Delay Testing Huawei LiZhongcheng LiYinghua Min OriginalPaper Pages: 477 - 485
Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy Said HamdiouiAd J. Van De Goor OriginalPaper Pages: 487 - 498
Dynamic Power Supply Current Testing of CMOS SRAMs Jian LiuRafic Z. MakkiAyman Kayssi OriginalPaper Pages: 499 - 511
Testing the Local Interconnect Resources of SRAM-Based FPGA's M. RenovellJ.M. PortalY. Zorian OriginalPaper Pages: 513 - 520
A Practical Vector Restoration Technique for Large Sequential Circuits Surendra K. BommuKiran B. DoreswamySrimat T. Chakradhar OriginalPaper Pages: 521 - 539
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time Irith PomeranzSudhakar M. Reddy OriginalPaper Pages: 541 - 552
A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency Satoshi OhtakeToshimitsu MasuzawaHideo Fujiwara OriginalPaper Pages: 553 - 566