Abstract
The usability of I DDQ testing is limited by the subthreshold currents of the low-V T, submicron MOS transistors in the low bias voltage circuits. The paper addresses the cooling of the chip in order to overcome this problem. Experimental results concerning the effect of cooling on the threshold voltage and subthreshold current are presented in the range of −75...25 Centigrade. The subthreshold currents decrease by a factor of about 100–1000 by cooling-down the chip to −75 Centigrade.
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V. Székely, M. Rencz, S. Török, and B. Courtois, “IDDQ Testing of Submicron CMOS by Cooling,” Seventh Asian Test Symposium (ATS'98), Singapore, Dec. 2-4, 1998.
V. Székely, M. Rencz, S. Török, and B. Courtois, “Cooling is a Possible Way to Extend the Usability of IDDQ Testing,” Electronics Letters, Vol. 33, No. 25, pp. 2117-2118, Dec. 1997.
T.W. Williams, R.H. Dennard, R. Kapur, M.R. Mercer, and W. Maly, “Iddq Testing for High Performance CMOS-The Next Ten Years,” European Design & Test Conference, March 1996, pp. 578-583.
T.W. Williams, R. Kapur, M.R. Mercer, R.H. Dennard, and W. Maly, “Iddq Test: Sensitivity Analysis of Scaling,” Proceedings of IEEE International Test Conference, Washington, USA, Oct. 20-25, 1996, pp. 786-792.
M. Sachdev, “Deep Sub-Micron IDDQTest Options,” Proceedings of IEEE International Test Conference, Washington, USA, Oct. 20-25, 1996, pp. 786-792.
M. Sachdev, “Deep Sub-Micron IDDQ Testing: Issues and Solutions,” Proceeding of European Design & Test Conference, Paris, France, March 17-20, 1997, pp. 271-278.
A. Keshavarzi, K. Roy, and C. Hawkins, “Intrinsic Leakage in Low Power Deep Submicron CMOS ICs,” Proceedings of ITC'97, Washington, USA, Nov. 1-6 1997, pp. 146-155.
C. Hawkins, A. Keshavarzi, and K. Roy, “High performance CMOS IC Challenges in IDDQ Testing, Compendium of Papers,” ETW98, Sitges, Barcelona, Spain, May 27-29, 1998, pp. 167-170.
N. Arora, MOSFET Models for VLSI Circuit Simulation, Springer Verlag, New York, 1993.
V. Székely, M. Rencz, S. Török, Cs. Márta, and L. Lipták-Fegó, “CMOS Temperature Sensors and Built-in Test Circuitry for Thermal Testing of ICs,” Sensors and Actuators, A. Physical, Vol. 71, No. 12, pp. 10-18, 1998.
S.M. Sze, Physics of Semiconductor Devices, John Wiley & Sons, New York, 1981.
E.A. Gutiérrez-D, J. De la Hidalga-W, M.J. Deen, and S.V. Koshevaya, “An Alternative Method to Monitor and Control the IC Temperature in the 4.2-77 K range,” Proceedings of ESSDERC'97, Stuttgart, Germany, Sept. 22-24 1997, pp. 436-439.
A. Pfahnl, J.H. Lienhard, and A.H. Slocum, “Temperature Control of a Handler Test Interface,” Proceedings of IEEE International Test Conference ITC'98, Washington, DC, USA, Oct. 18-23, 1998, pp. 114-118.
M. Malinoski, J. Maveety, S. Knostman, and T. Jones, “A Test Site Thermal Control System for At-Speed Manufacturing Testing,” Proceedings of IEEE International Test Conference, ITC'98, Washington, DC, USA, Oct. 18-23, 1998, pp. 119-128.
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Rencz, M., Székely, V., Török, S. et al. IDDQ Testing of Submicron CMOS—by Cooling?. Journal of Electronic Testing 16, 453–461 (2000). https://doi.org/10.1023/A:1008364515030
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DOI: https://doi.org/10.1023/A:1008364515030