1. Editorial

   • Vishwani D. Agrawal

   OriginalPaper Pages: 5 - 5

2. Test Technology Technical Council Newsletter

   OriginalPaper Pages: 7 - 8

3. Guest Editorial

   • Michael Nicolaidis
   • Rob Roy

   OriginalPaper Pages: 9 - 9

4. Effect of Noise on Analog Circuit Testing

   • Madhu K. Iyer
   • M.L. Bushnell

   OriginalPaper Pages: 11 - 22

5. Decreasing the Sensitivity of ADC Test Parameters by Means of Wobbling

   • R. De Vries
   • A.J.E.M. Janssen

   OriginalPaper Pages: 23 - 29

6. Mixed Signal DFT at GHz Frequencies

   • R. Mason
   • S. Ma

   OriginalPaper Pages: 31 - 39

7. Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems

   • F.M. Gonçalves
   • J.P. Teixeira

   OriginalPaper Pages: 41 - 52

8. IDDQ Testing of Opens in CMOS SRAMs

   • Victor H. Champac
   • José Castillejos
   • Joan Figueras

   OriginalPaper Pages: 53 - 62

9. New Techniques for Deterministic Test Pattern Generation

   • Ilker Hamzaoglu
   • Janak H. Patel

   OriginalPaper Pages: 63 - 73

10. Efficient Path Selection for Delay Testing Based on Path Clustering

    • Seiichiro Tani
    • Mitsuo Teramoto
    • Kazuyoshi Matsuhiro

    OriginalPaper Pages: 75 - 85

11. A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing

    • E.S. Sogomonyan
    • A.D. Singh
    • M. Goessel

    OriginalPaper Pages: 87 - 96

12. Deterministic Built-in Pattern Generation for Sequential Circuits

    • Vikram Iyengar
    • Krishnendu Chakrabarty
    • Brian T. Murray

    OriginalPaper Pages: 97 - 114

13. Self-Timed Boundary-Scan Cells for Multi-Chip Module Test

    • T.A. García
    • A.J. Acosta
    • J.L. Huertas

    OriginalPaper Pages: 115 - 127

14. Structural Fault Testing of Embedded Cores Using Pipelining

    • M. Nourani
    • C.A. Papachristou

    OriginalPaper Pages: 129 - 144

15. Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes

    • Debaleena Das
    • Nur A. Touba

    OriginalPaper Pages: 145 - 155

16. Adaptive Fault Detection and Diagnosis of RAM Interconnects

    • Jun Zhao
    • Fred J. Meyer
    • Fabrizio Lombardi

    OriginalPaper Pages: 157 - 171

17. On Design Validation Using Verification Technology

    • Dinos Moundanos
    • Jacob A. Abraham

    OriginalPaper Pages: 173 - 189

18. Experience in Validation of PowerPCTM Microprocessor Embedded Arrays

    • Li-C. Wang
    • Magdy S. Abadir

    OriginalPaper Pages: 191 - 205