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6-T and 7-T SRAM CELL Design Using Doping-Less Charge Plasma TFET

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Abstract

Charge plasma based doping-less tunnel FETs (DLTFETs) are attracting attention for providing reduced leakage currents and high ION/IOFF ratio. In this work, a new GaAs based gate stack charge plasma doping-less tunnel FET (GaAs based GSDLTFET) has been proposed. The simulation results show that the proposed device gives higher ION/IOFF ratio in comparison to DLTFETs due to high mobility of the GaAs substrate. Various SRAM circuits have been designed and analyzed using DLTFET and GaAs based GSDLTFET viz. 6 T standard SRAM, 6 T TFET SRAM and 7 T TFET SRAM. The circuit analysis shows that SRAM cell designed using GaAs based GSDLTFET provides better noise margins in comparison to DLTFET based SRAMs due to high ION/IOFF ratio. Standby leakage power is also reduced in DLTFETs as compared to CMOS. Due to the enhanced noise margins and reduced leakage power our proposed GaAs based GSDLTFET can be used to design energy- efficient memory devices.

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Authors and Affiliations

  1. National Institute of Technology, Jalandhar, Punjab, 144011, India

    Harsimran Kaur & R. K. Sarin

  2. Amity University, Noida, Uttar Pradesh, 201313, India

    Sunny Anand

  3. Jamia Millia Islamia, New Delhi, Delhi, 110025, India

    S. Intekhab Amin

Authors
  1. Harsimran Kaur
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  2. R. K. Sarin
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  3. Sunny Anand
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  4. S. Intekhab Amin
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Correspondence to Sunny Anand.

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Kaur, H., Sarin, R.K., Anand, S. et al. 6-T and 7-T SRAM CELL Design Using Doping-Less Charge Plasma TFET. Silicon 13, 4091–4100 (2021). https://doi.org/10.1007/s12633-020-00713-w

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