Skip to main content
SpringerLink
Log in

A Novel Metal Dielectric Metal Based GAA-Junction-Less TFET Structure for Low Loss SRAM Design

  • Original Paper
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

This paper investigates the performance of the gate all around junction-less tunnel field effect transistor (GAA-JLTFET) device with Metal-dielectric-metal–insulator-semiconductor (MDMIS) configuration for low leakage SRAM design. The proposed device structure (MDMIS-GAA-JLTFET) effectively suppresses the subthreshold swing (SS) of the transistor and produces a lower SS of 15 mV/decade. The use of high-k dielectric layer generates a high on current of 1.69 mA/µm, and supress an off current up to 10–18 A/µm which results due to blocking of source tunnelling current in the off-state. The effect of high-k dielectric is optimized using ATLAS tool to make sure that the proposed device structure is capable for low leakage SRAM design. The use of high-k material as an insulator in MDMIS structure assured it to be used in low leakage memory system. The promising capability of proposed structure makes the 6 T- SRAM cell structure lossless. Further, the simulated SRAM cell is compared with CMOS based SRAM which ensures that’s the proposed MDMIS based SRAM is suitable for low leakage memory system.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Nikonov IY (2015) Benchmarking of beyond-CMOS exploratory devices for logic integrated circuits. IEEE. J Explor Solid-State Comput Devices Circuits 1:3–11

    Article  Google Scholar 

  2. Ionescu A, Riel H (2011) Tunnel field-effect transistors as energy efficient electronic switches. Nature 479:329–337

    Article  CAS  PubMed  Google Scholar 

  3. Su P, Goto K (2002) A thermal activation view of low voltage impact ionization in MOSFETs. IEEE Electron Device Lett 23(9):550–552

    Article  Google Scholar 

  4. Asra R, Shrivastava M, Murali KV (2011) A tunnel FET for Vdd scaling below 0.6 V with a CMOS-comparable performance. IEEE Trans Electron Devices 58(7):1855–1863

    Article  Google Scholar 

  5. Gupta N, Kumar A (2021) Numerical assessment of high-k spacer on symmetric S/D underlap GAA junctionless accumulation mode silicon nanowire MOSFET for RFIC design. Appl Phys A 127:76

    Article  CAS  Google Scholar 

  6. Cho S, Lee JS, Rok K (2011) Analyses on small – signal parameters and radio-frequency modeling of gate-all-around tunneling field effect transistors. IEEE Trans Electron Devices 58(12):4164–4171

    Article  Google Scholar 

  7. Wang Z, Chang S, Yue Hu, He H, He J (2014) A novel barrier controlled tunnel FET. IEEE Electron Device Lett 35(7):798–800

    Article  CAS  Google Scholar 

  8. Agarwal S, Klimeck G (2010) Leakage- reduction design concepts for low-power vertical tunneling field- effect transistors. IEEE Electron Device Lett 31(6):621–623

    Article  CAS  Google Scholar 

  9. Kawale R, Pachouri A, Singh Y, Agarwal L (2021) Design of TFET with ferroelectric gate material for low power applications. 2021 First International Conference onAdvances in Computing and Future Communication Technologies (ICACFCT), pp 110–113

  10. Lee JS, Seo JH, Cho S, Lee J-H, Kang S-W, Bae J-H, Cho E-S, Kang IM (2013) Simulation study on effect of drain underlap in gate-all-around tunneling field-effect transistors. Curr Appl Phys 13(6):1143–1149

    Article  Google Scholar 

  11. Fiore A, Franco J, Cho M, Crupi F, Strangio S, Roussel PJ, Rooyackers R, Collaert N, Linten D (2017) Single defect discharge events in vertical-nanowire tunnel FETs. IEEE Trans Device Mater Reliab 17(1):253–258

    Article  CAS  Google Scholar 

  12. Abdi DB, Jagadesh Kumar M (2015) PNPN tunnel FET with controllable drain side tunnel barrier width: Proposal and analysis. Superlattices Microstruct 86:121–125

    Article  CAS  Google Scholar 

  13. Sze SM, Ng KK (2006) Physics of Semiconductor Devices. Wiley, London

    Book  Google Scholar 

  14. E P, B PK, B C et al (2022) A comprehensive review of recent progress, prospect and challenges of silicon carbide and its applications. Silicon

  15. Damrongplasit N, Kim SH, Liu TJK (2013) Study of random dopant fluctuation induced variability in the raised-Ge-source TFET. IEEE Electron Dev Lett 34(2):184–186

    Article  CAS  Google Scholar 

  16. Sahay S, Kumar MJ (2015) Controlling the drain side tunneling width to reduce ambipolar current in tunnel FETs using hetero dielectric BOX. IEEE Trans Electron Devices 62(11):3882–3886

    Article  Google Scholar 

  17. Colinge J-P, Lee C-W, Afzalian A, Akhavan ND, Yan R, Ferain I, Ravazi P, O’Neill B, Blake A, White M, Kelleher A-M, McCarthy B, Murphy R (2010) Nanowire transistors without junctions. Nat Nanotechnol 5(3):225–229

    Article  CAS  PubMed  Google Scholar 

  18. Abdi DB, Jagadesh Kumar M (2014) Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain. IEEE J Electron Devices Soc 2(6):187–190

    Article  Google Scholar 

  19. Kumar K, Kumar A, Mishra V (2022) Correction to: implementation of band gap and gate oxide engineering to improve the electrical performance of SiGe/InAs charged plasma-based junctionless-TFET. Silicon 25:1–11. https://doi.org/10.1007/s12633-022-02132-5

  20. Boucart K, Ionescu AM (2017) Double-gate tunnel FET with High-k gate dielectric. IEEE Trans on Electron Devices 54(7):1725–1733

    Article  Google Scholar 

  21. Saeidi A, Jazaeri A (2016) Double-gate negative-capacitance MOSFET with PZT gate-stack on ultra-thin body SOI: An experimentally calibrated simulation study of device performance. IEEE Trans Electron Devices 63(12):4678–4684

    Article  Google Scholar 

  22. Preethi S, Venkatesh M, Karthigai Pandian M, Lakshmi PG (2021) Analytical modeling and simulation of gate-all-around junctionless mosfet for biosensing applications. SILICON 13:3755–3764. https://doi.org/10.1007/s12633-021-01301-2

    Article  CAS  Google Scholar 

  23. Saeidi A, Jazaeri F, Beland F (2017) Negative capacitance as performance booster for tunnel FETs and MOSFETs: an experimental study. IEEE Electron Device Lett 38(10):1485–1488

    Article  CAS  Google Scholar 

  24. Sahay S, Kumar MJ (2017) Diameter dependence of leakage current in nanowire junctionless field effect transistors. IEEE Transactions on Electron Device 64(3):1330–1335

    Article  Google Scholar 

  25. Dutta U, Soni MK (2017) Design & optimization of gate-all-around tunnel FET for low power applications. Int J Eng Tech 7(4):2263–2267

    Article  Google Scholar 

  26. Vadizadeh M (2021) Digital performance assessment of the dual-material gate GaAs/InAs/Ge junctionless TFET. IEEE Trans Electron Devices 68(4):1986–1991

    Article  CAS  Google Scholar 

  27. Priya GL, Balamurugan NB (2018) Gate-all-around junctionless tunnel FET with germanium and High-K gate dielectric material FET. Informacije MIDEM J Microelectron Electron Components Mater 48:53–61

    Google Scholar 

  28. Saraswathi D, Balamurugan NB, Priya GL, Manikandan S (2015) A compact analytical model for 2D triple material surrounding gate nanowire tunnel field effect transistors 2015. Intelligent Computing and Applications. Advances in Intelligent Systems and Computing, vol 343. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2268-2_35

  29. Bal P, Akram MW, Mondal P, Ghosh B (2013) Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET). J Comput Electron 12:782–878

    Article  Google Scholar 

  30. Bangsaruntip S, Cheng SL (2013) Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond. IEEE Int Electron Devices Meeting 20–4

  31. Saeidi A, Rosca T, Memisevic M (2020) Nanowire tunnel FET with simultaneously reduced subthermionic subthreshold swing and off-current due to negative capacitance and voltage pinning effects. Nano Lett 20(5):3255–3262

    Article  CAS  PubMed  PubMed Central  Google Scholar 

  32. Priya GL, Venkatesh M, Balamurugan NB, Samuel TSA (2021) Triple metal surrounding gate junctionless tunnel FET based 6T SRAM design for low leakage memory system. SILICON 13:1691–1702

    Article  CAS  Google Scholar 

  33. Priya GL, B NB (2020) Improvement of subthreshold characteristics of dopingless tunnel FET using hetero gate dielectric material: analytical modeling and simulation. Silicon 12(9):2189–2201

  34. Priya GL, Balamurugan NB (2019) New dual material double gate junctionless tunnel FET: Subthreshold modeling and simulation. AEU Int J Electron Commun 99:130–138

    Article  Google Scholar 

  35. Cao W, Sarkar D, Khatami Y, Kang J, Banerjee K (2014) Subthreshold-swing physics of tunnel field-effect transistors. AIP Adv 4:067141

    Article  Google Scholar 

  36. Merad F, Guen-Bouazza A (2020) DC performance analysis of a 20 nm gate length n-type Silicon GAA junctionless (Si-JL-GAA) transistor. Int J Electr Comput Eng (IJECE) 10(4):4043–4405

    Article  Google Scholar 

  37. Strangio S et al (2015) Impact of TFET unidirectionality and ambipolarity on the performance of 6T SRAM cells. IEEE J Electron Devices Soc 3(3):223–232

    Article  Google Scholar 

  38. Kaur H et al (2021) 6-T and 7-T SRAM cell design using doping-less charge plasma TFET. SILICON 13(11):4091–4100

    Article  CAS  Google Scholar 

  39. Gopal G, Varma T (2022) Simulation-based analysis of ultra thin-body double gate ferroelectric TFET for an enhanced electric performance. Silicon 14:6553–6563

    Article  CAS  Google Scholar 

  40. Liu J-S, Clavel MB, Hudait MK (2017) An energy-efficient tensile-strained Ge/InGaAs TFET 7T SRAM cell architecture for ultralow-voltage applications. IEEE Trans Electron Devices 64(5):2193–2200

    Article  CAS  Google Scholar 

  41. Rajasekharan B, Hueting RJE, Salm C, van Hemert T, Wolters RAM, Schmitz J (2010) Fabrication and characterization of the charge-plasma diode. IEEE Electron Device Lett 31(6):528–530

    Article  CAS  Google Scholar 

  42. Vijh M, Gupta RS, Pandey S (2019) Graphene based tunnel field effect transistor for RF applications. 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring): 256–259

Download references

Acknowledgements

Authors are thankful to MNNIT Allahabad for accessing the SILVACO software for simulation.

Author information

Authors and Affiliations

  1. School of Electronics Engineering, Vellore Institute of Technology, Chennai, 600127, India

    Lucky Agarwal, G. Lakshmi Priya, E. Papnassam & B. Prashanth Kumar

  2. Centre for Innovation and Product Development, Vellore Institute of Technology, Chennai, 600127, India

    G. Lakshmi Priya

  3. Department of ECE, CMR Institute of Technology, Bangalore, 560037, India

    M. Venkatesh

Authors
  1. Lucky Agarwal
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. G. Lakshmi Priya
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. E. Papnassam
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. B. Prashanth Kumar
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. M. Venkatesh
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

First author has done the literature survey, simulation and prepared the manuscript.

Second author has contributed towards the low loss memory application.

Third author has contributed towards significantly contributed in the introduction section of the manuscript.

Fourth author has given valuable suggestions and done the overall correction of the manuscript.

Fifth author has contributed towards simulation of low loss SRAM cell.

Corresponding author

Correspondence to Lucky Agarwal.

Ethics declarations

Consent to participate

Not applicable.

Consent for Publication

Not applicable.

Conflicts of interest/Competing interests

The authors have no conflict of interest.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Agarwal, L., Priya, G.L., Papnassam, E. et al. A Novel Metal Dielectric Metal Based GAA-Junction-Less TFET Structure for Low Loss SRAM Design. Silicon 15, 2989–3001 (2023). https://doi.org/10.1007/s12633-022-02218-0

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-022-02218-0

Keywords

Search

Navigation