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Triple Metal Surrounding Gate Junctionless Tunnel FET Based 6T SRAM Design for Low Leakage Memory System

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Abstract

The promising capability of Triple Material Surrounding Gate Junctionless Tunnel FET (TMSG – JL – TFET) based 6 T SRAM structure is demonstrated by employing Germanium (Ge) and High-K gate dielectric material. The high – K insulation guarantees the proposed device to be used in low leakage memory systems. The corresponding analytical model is developed to extract various device parameters such as surface potential, electric field and threshold voltage. The results yield minimization of hot carrier effects at the drain end, when compared to conventional Silicon (Si) based Tunnel FETs (TFETs). Further, the ambipolar characteristics of the proposed device is explored and 6 T Ge – TMS – SG – JL – TFET based SRAM design is proposed. The results are compared with CMOS based SRAM and the analytical model presented is validated using 3D - TCAD ATLAS simulation, which ensures the accuracy and exactness of the developed model.

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Acknowledgments

We thank the anonymous referees for their useful suggestions.

Availability of Data and Material

There are no linked research data sets for this submission. The following reason is given: No data was used for the research described in the article.

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Not Applicable.

Funding

The authors of the manuscript did not receive any funding, grants, or in-kind support in support of the research or the preparation of the manuscript.

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Authors and Affiliations

  1. School of Electronics Engineering (SENSE), VIT University, Chennai, Tamil Nadu, 600127, India

    G. Lakshmi Priya

  2. Department of ECE, M. Kumarasamy College of Engineering, Karur, Tamil Nadu, 639113, India

    M. Venkatesh

  3. Department of ECE, Thiagarajar College of Engineering, Madurai, Tamil Nadu, 625015, India

    N. B. Balamurugan

  4. Department of ECE, National Engineering College, Kovilpatti, Tamil Nadu, 628503, India

    T. S. Arun Samuel

Authors
  1. G. Lakshmi Priya
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  2. M. Venkatesh
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  3. N. B. Balamurugan
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  4. T. S. Arun Samuel
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Contributions

Author 1 (G. Lakshmi Priya): Conceived and design the analysis, contributed data and analysis tools, and wrote the paper. Author 2 (M. Venkatesh): Performed the analysis, calibrated the results, and wrote the paper. Author 3 (N. B. Balamurugan): Worked in TCAD portion of the proposed device, Experimental data analysis. Author 4 (T. S. Arun Samuel): Worked in TCAD simulation of SRAM design, and wrote the paper for the corresponding portion.

Corresponding author

Correspondence to G. Lakshmi Priya.

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Conflict of Interest

All authors have participated in (a) conception and design, or analysis and interpretation of the data; (b) drafting the article or revising it critically for important intellectual content; and (c) approval of the final version. This manuscript has not been submitted to, nor is under review at, another journal or other publishing venue. The authors have no affiliation with any organization with a direct orindirect financial interest in the subject matter discussed in the manuscript.

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Priya, G.L., Venkatesh, M., Balamurugan, N.B. et al. Triple Metal Surrounding Gate Junctionless Tunnel FET Based 6T SRAM Design for Low Leakage Memory System. Silicon 13, 1691–1702 (2021). https://doi.org/10.1007/s12633-021-01075-7

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