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1.4kV Planar Gate Superjunction IGBT with Stepped Doping Profile in Drift and Collector Region

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Abstract

In this paper, stepped doping profile in alternate pillars and collector region of superjunction IGBT structure is presented. The proposed device structure consists of lightly and heavily doped region in upper and lower part of drift region. In addition to this, the collector layer doping concentration reduces along the x-direction. The initiation point of avalanche multiplication shifts from top and bottom corners to middle of the drift region. Due to this structural design, we have revealed that the area specific on resistance of proposed device is reduced by 16% at 300 K and 10% at 400 K without affecting breakdown voltage. Simulation results determine that 34.9% reduction in miller capacitance at room temperature in propose device. Additionally, 40% improvement in switching delay and 17% reduction in turn-off time is resulted. Baliga’s Figure of Merit (BFOM) and other technology Figure of Merit (FOM) are improved by 19% and 38% respectively. Furthermore, Eoff is reduced by 17.84% in proposed device.

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  1. Department of Electronics and Telecommunication, NIT Raipur, Amanaka, Raipur, Chhattisgarh 492010, India

    Namrata Gupta & Alok Naugarhiya

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  1. Namrata Gupta
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  2. Alok Naugarhiya
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Correspondence to Namrata Gupta.

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Gupta, N., Naugarhiya, A. 1.4kV Planar Gate Superjunction IGBT with Stepped Doping Profile in Drift and Collector Region. Silicon 13, 697–706 (2021). https://doi.org/10.1007/s12633-020-00456-8

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