Gaussian Doped Planar 4H-SiC Junctionless Field Effect Transistor For Enhanced Gate Controllability

Abstract

The incorporation of gaussian/multiple peak gaussian doping in planar 4H-SiC junctionless field effect transistor (JLFET) allows the conceptualization and realization of higher gate controllablity. With the aim of formulating and investigating the underlying device current gating mechanism of gaussian/multiple peak gaussian doping 4H-SiC JLFET with enhanced device performance, we have adopted the exhaustive calibrated 2D TCAD study approach. Our study suggests that by deploying either gaussian or multiple peak gaussian doping improves the I_ON/I_OFF ratio magnificently as compared to the uniformly doped planar 4H-SiC JLFET. Moreover, multiple peak gaussian doping even without the use of P⁺ pockets improves the switching behaviour as the sub-threshold slope (SS) value reduces. Interestingly, it is observed that just by incorporating the gaussian doping approach the mandate of incorporating P⁺ pockets to get better volume depletion can be relaxed. Thus the additional fabrication steps to realize the P⁺ pockets in junctionless structure can be avoided. This results in the lowering of device thermal budget and random dopant fluctuations (RDFs) immune structure. Further, as the reported device demonstrates volume/bulk conduction, it is also expected to be immune towards the interface trapped charges, hence this device realization no more needs additional fabrication steps such as counter doping and annealing to neutralize the semiconductor-oxide traps. Further, device sensitivity analysis in terms of channel length, P⁺ pockets length, fixed trapped charges at the 4H-SiC-SiO₂ interface and temperature variation has also been carried out here.