Abstract
A novel LDMOS device featured with Super Junction (SJ) and Extended Triple Gate (ETG) is proposed, named ETG LDMOS is demonstrated by the numerical simulation. The ETG consists of a planner gate and two extended side gates. The side gates are formed the P-Pillar/Oxide/drift sandwich structure. Moreover, the side gates consist of two back-to-back P-Pillar/N-Pillar diodes which connected by the float ohmic contact. The anode of D1 is shortly connected with the Gate electrode, and the Cathode of D2 is shortly connected with the Drain electrode. At the OFF-state, the Source Potential and Gate Potential are equal (\( {V}_{\varvec{S}}={V}_{\varvec{G}}=\textbf{0}, {V}_{\varvec{GD}}<\textbf{0}\)), the D1 is blocked and sustain the negative \({V}_{\varvec{GD}}\) while the D2 is turn-on. The P-Pillar1 can be fully depleted and assisted to reduce the Internal electric field of the N-Pillar. Thus, the Breakdown Voltage (BV) of the device can be greatly enhanced. At the ON- state, the gate apply positive voltage, then \({V}_{\varvec{GD}}>\textbf{0}\), the D1 is turn-on and extended the gate voltage in the P-Pillar1 while the D2 is blocked. Then, the charge accumulation besides the side gates formed the extended channel. Consequently, the specific ON-resistance (\({R}_{\varvec{ON,sp}}\)) of the device can be decreased remarkably. As a result, the ETG achieves superior \({BV}-{R}_{\varvec{ON,sp}}\) trade-off relationship. Additionally, the Figured-On-Merit (FOM) is up to 29 MW/cm\(^\textbf{2}\).
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The data that support the findings of this study are openly available in the reference [17].
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National Nature Science Foundation of China (Grants Nos.61604027). The Key scientific research project of Chongqing Municipal Education Commission under Grants KJZD-K202300610.
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Y.H wrote the main manuscript text, W.C and Z.D made revision to the article. Y.H contributed to contributed to the study conception and design. The first draft of the manuscript was written by Y.H, W.C and Z.D commented on previous versions of the manuscript. All authors read and approved the final manuscript.
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He, Y., Chen, W. & Duan, Z. A Superjunction Extended Triple Gate LDMOS with Charge Accumulation Effect. Silicon 16, 1703–1711 (2024). https://doi.org/10.1007/s12633-023-02788-7
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DOI: https://doi.org/10.1007/s12633-023-02788-7