Abstract
Floating-point (FP) multipliers are the main energy consumers in many modern embedded digital signal processing (DSP) and multimedia systems. For lossy applications, minimizing the precision of FP multiplication operations under the acceptable accuracy loss is a well-known approach for reducing the energy consumption of FP multipliers. This paper proposes a multiple-precision FP multiplier to efficiently trade the energy consumption with the output quality. The proposed FP multiplier can perform low-precision multiplication that generates 8−, 14−, 20−, or 26-bit mantissa product through an iterative and truncated modified Booth multiplier. Energy saving for low-precision multiplication is achieved by partially suppressing the computation of mantissa multiplier. In addition, the proposed multiplier allows the bitwidth of mantissa in the multiplicand, multiplier, and output product to be dynamically changed when it performs different FP multiplication operations to further reduce energy consumption. Experimental results show that the proposed multiplier can achieve 59 %, 71 %, 73 %, and 82 % energy saving under 0.1 %, 1 %, 5 %, and 11 % accuracy loss, respectively, for the RGB-to-YUV & YUV-to-RGB conversion when compared to the conventional IEEE single-precision multiplier. In addition, the results also exhibit that the proposed multiplier can obtain more energy reduction than previous multiple-precision iterative FP multipliers.
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References
IEEE. (1985). Standard for binary floating-point arithmetic (pp. 754–1985). New York: ANSI/IEEE.
Yu, R.K., & Zyner, G.B. (1995). 167 MHz radix-4 floating point multiplier. Proceedings of the 12th Symposium on Computer Arithmetic, pp. 149–154.
Quach, N., Takagi, N., & Flynn, M. (1991). On fast IEEE rounding. Stanford: Stanford University. Technical Report: CSL-TR-91-459.
Even, G., & Seidel, P. M. (2000). A comparison of three rounding algorithms for IEEE floating-point multiplication. IEEE Transactions on Computers, 49(7), 638–650.
Quach, N. T., Takagi, N., & Flynn, M. J. (2004). Systematic IEEE rounding method for high-speed floating-point multipliers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(5), 511–521.
Wires, K. E., Schulte, M. J., & Stine, J. E. (2000). Variable-correction truncated floating point multipliers. Proceedings of the 34th Asilomar Conference on Signals Systems and Computers, 2, 1344–1348.
Tong, J. Y. F., Nagle, D., & Rutenbar, R. A. (2000). Reducing power by optimizing the necessary precision/range of floating-point arithmetic. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8(3), 273–286.
Visalli, G., & Pappalardo, F. (2003). Low-power floating-point encoding for signal processing applications. Proceedings of the IEEE Workshop on Signal Processing Systems, pp.292–297.
Jo, M., Prasad Arava, V.K., Yang, H., & Choi, K. (2007). Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecture. Proceedings of the IEEE International SOC Conference, pp. 127–130.
Pool, J., Lastra, A., & Singh, M. (2008). Energy-precision tradeoffs in mobile graphics processing units. Proceedings of the IEEE International Conference on Computer Design, pp. 60–67.
Choi, J., Jeon, J., & Choi, K. (2000). Power minimization of functional units by partially guarded computation. Proceedings of the International Symposium on Low Power Electronics and Design, pp.131–136.
Huang, Z., & Ercegovac, M. D. (2002). Two-dimensional signal gating for low-power array multiplier design. Proceedings of the IEEE International Symposium on Circuits and Systems, 1, 489–492.
Ling, W., & Savaria, Y. (2004). Variable-Precision Multiplier for Equalizer with Adaptive Modulation. Proceedings of the 47th IEEE International Midwest Symposium on Circuits and Systems, 1, 553–556.
Sjalander, M., Drazdziulis, M., Larsson-Edefors, P., & Eriksson, H. (2005). A low-leakage twin-precision multiplier using reconfigurable power gating. Proceedings of the IEEE International Symposium on Circuits and Systems, 2, 1654–1657.
Krithivasan, S., & Schulte, M. J. (2003). Multiplier architectures for media processing. Proceedings of the 37th Asilomar Conference on Signals Systems and Computers, 2, 2193–2197.
Mokrian, P., Ahmadi, M., Jullien, G., & Miller, W.C. (2003). A reconfigurable digit multiplier architecture. Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, pp. 125–128.
Wey, C.L., & Li, J.F. (2004). Design of reconfigurable array multipliers and multiplier-accumulators. Proceedings of the IEEE Asia-Pacific Conference on Circuits and Systems, pp. 37–40.
Quan, S., Qiang, Q., & Wey, C.L. (2005). A novel reconfigurable architecture of low-power unsigned multiplier for digital signal processing. Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3327–3330.
Tan, D., Lemonds, C. E., & Schulte, M. J. (2009). Low-power multiple-precision iterative floating-point multiplier with SIMD support. IEEE Transactions on Computers, 58(2), 175–187.
Wires, K.E., Schulte, M.J., & Stine, J.E. (2001). Combined IEEE compliant and truncated floating point multipliers for reduced power dissipation. Proceedings of the International Conference on Computer Design, pp. 497–500.
Lim, Y. C. (1992). Single-precision multiplier with reduced circuit complexity for signal processing applications. IEEE Transactions on Computers, 41(10), 1333–1336.
Schulte, M. J., & Swartzlander, E. E., Jr. (1993). Truncated multiplication with correction constant. Proceedings of the Workshop on VLSI Signal Processing, VI, 388–396.
Cho, K. J., Lee, K. C., Chung, J. G., & Parhi, K. K. (2004). Design Low-error fixed-width modified booth multiplier. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(5), 522–531.
Hartley, R. I., & Parhi, K. K. (1995). Digit-serial computation. Norwell: Kluwer Academic.
Even, G., Mueller, S.M., & Seidel, P.M. (1997). A dual mode IEEE multiplier. Proceedings of the 2nd Annual IEEE International Conference on Innovative Systems in Silicon, pp. 282–289.
Usami, K., Nakata, M., Shirai, T., Takeda, S., Seki, N., Amano, H., & Nakamura, H. (2009). Implementation and evaluation of fine-grain run-time power gating for a multiplier. Proceedings of the IEEE International Conference on IC Design and Technology, pp. 7–10.
Chowdhury, M.H., Gjanci, J., & Khaled, P. (2008). Innovative power gating for leakage reduction. Proceedings of the IEEE International Symposium on Circuits Systems, pp. 1568–1571.
Wen, M. C., Wang, S. J., & Lin, Y. N. (2005). Low-power parallel multiplier with column bypassing. Electronics Letters, 41(10), 581–583.
Huang, Z., & Ercegovac, M. D. (2005). High-performance low-power left-to-right array multiplier design. IEEE Transactions on Computers, 54(3), 272–283.
Wu, K.Y., Liang, J.Y., Yu, K.K., & Kuang, S.R. (2011). An exact error analysis method for multi-mode floating point iterative booth multiplier. 2011 World Congress on Engineering and Technology.
Acknowledgments
This work was supported in part by the National Science Council, Taiwan, under Grant NSC 98-2220-E-110-006. The authors would like to thank the National Chip Implementation Center, Taiwan, for their contributions and support in technology data.
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Kuang, SR., Wu, KY. & Yu, KK. Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications. J Sign Process Syst 72, 43–55 (2013). https://doi.org/10.1007/s11265-012-0695-1
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DOI: https://doi.org/10.1007/s11265-012-0695-1