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A Precision-Aware Neuron Engine for DNN Accelerators

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Abstract

Deep Neural Networks (DNNs) form the backbone of contemporary deep learning, powering various artificial intelligence (AI) applications. However, their computational demands, primarily stemming from the resource-intensive Neuron Engine (NE), present a critical challenge. This NE comprises of Multiply-and-Accumulate (MAC) and Activation Function (AF) operations, contributing significantly to the overall computational overhead. To address these challenges, we propose a groundbreaking Precision-aware Neuron Engine (PNE) architecture, introducing a novel approach to low-bit and high-bit precision computations with minimal resource utilization. The PNE’s MAC unit stands out for its innovative pre-loading of the accumulator register with a bias value, eliminating the need for additional components like an extra adder, multiplexer, and bias register. This design achieves significant resource savings, with an 8-bit signed fixed-point implementation demonstrating notable reductions in resource utilization, critical delay, and power-delay product compared to conventional architectures. An 8-bit sfixed < N, q > implementation of the MAC in the PNE shows 29.23% savings in resource utilization and 32.91% savings in critical delay compared with IEEE architecture, and 24.91% savings in PDP (power-delay product) compared with booth architecture. Our comprehensive evaluation showcases the PNE’s efficacy in maintaining inferential accuracy across quantized and unquantized models. The proposed design not only achieves precision-awareness with a minimal increase (\(\approx\) 10%) in resource overhead, but also achieves a remarkable 34.61% increase in throughput and reduction in critical delay (34.37% faster than conventional design), highlighting its efficiency gains and superior performance in PNE computations. Software emulator shows minimal accuracy losses ranging from 0.6% to 1.6%, the PNE proves its versatility across different precisions and datasets, including MNIST (on LeNet) and ImageNet (on CaffeNet). The flexibility and configurability of the PNE make it a promising solution for precision-aware neuron processing, particularly in edge AI applications with stringent hardware constraints. This research contributes a pivotal advancement towards enhancing the efficiency of DNN computations through precision-aware architecture, paving the way for more resource-efficient and high-performance AI systems.

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Data Availability

Data sharing is not applicable to this article as no data sets were generated or analyzed during the current study, and detailed circuit simulation results are given in the manuscript.

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Acknowledgements

This article is an extended version of our previous conference paper presented at [10].

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Author notes

  1. Sudheer Vishwakarma and Gopal Raut have contributed equally to this work.

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Oriental University, Indore, India

    Sudheer Vishwakarma & Dhruva Ghai

  2. Department of Electrical Engineering, Indian Institute of Technology Indore, Indore, India

    Gopal Raut, Sonu Jaiswal & Santosh Kumar Vishvakarma

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  1. Sudheer Vishwakarma
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  2. Gopal Raut
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Correspondence to Dhruva Ghai.

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Vishwakarma, S., Raut, G., Jaiswal, S. et al. A Precision-Aware Neuron Engine for DNN Accelerators. SN COMPUT. SCI. 5, 494 (2024). https://doi.org/10.1007/s42979-024-02851-z

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