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Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay

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Abstract

Power-supply noise is one of the major contributing factor for yield loss in sub-micron designs. Excessive switching in test mode causes supply voltage to droop more than in functional mode leading to failures in delay tests that would not occur otherwise under normal operation. Thus, there exists a need to accurately estimate on-chip supply noise early in the design phase to meet power requirements in normal mode and during test to prevent overstimulation during the test cycle and avoid false failures. Simultaneous switching activity (SSA) of several logic components is one of the main sources of power-supply noise (PSN) which results in reduction of supply voltages at the power-supplies of the logic gates. Most existing techniques and tools predict static IR-drop, which accounts for only part of the total voltage drop on the power grid. To our knowledge, inductive drop is not included in current noise analysis for simplification. The power delivery networks in today’s very deep-submicron chips are susceptible to slight variations and cause sudden large current spikes leading to higher Ldi ⁄ dt than resistive drop essentiating the need to account for this drop. Power-supply noise also impacts circuit operation incurring a significant increase in path delays. However, it is infeasible to carry out full-chip SPICE-level simulations on a design to validate the ATPG generated test patterns. Accurate and efficient techniques are required to quantify supply noise and its impact on path delays to ensure reliable operation in both mission mode and during test. We present a scalable current-based dynamic method to estimate both IR and Ldi / dt drop caused by simultaneous switching activity and use the technique to predict the increase in path delay. Our technique uses simulations of individual extracted paths in comparison to time-consuming full-chip simulations and thus it can be integrated with existing ATPG tools. The method uses these path simulations and a convolution-based technique to estimate power-supply noise and path delays. Simulation results for combinational and sequential benchmark circuits are presented demonstrating the effectiveness of our techniques.

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Authors and Affiliations

  1. Department of CSEE, University of Maryland, Baltimore County, ITE 317, CSEE Dept., 1000 Hilltop Circle, Baltimore, MD, 21250, USA

    Sushmita Kadiyala Rao

  2. Department of CSEE, University of Maryland, Baltimore County, ITE 316, CSEE Dept., 1000 Hilltop Circle, Baltimore, MD, 21250, USA

    Ryan Robucci

  3. Department of CSEE, University of Maryland, Baltimore County, ITE 322, CSEE Dept., 1000 Hilltop Circle, Baltimore, MD, 21250, USA

    Chintan Patel

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  1. Sushmita Kadiyala Rao
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  2. Ryan Robucci
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  3. Chintan Patel
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Correspondence to Sushmita Kadiyala Rao.

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Responsible editor: M. Tehranipoor

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Kadiyala Rao, S., Robucci, R. & Patel, C. Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay. J Electron Test 30, 125–147 (2014). https://doi.org/10.1007/s10836-013-5425-5

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  • DOI: https://doi.org/10.1007/s10836-013-5425-5

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