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A novel online offset-cancellation mechanism in a low-power 6-bit 2GS/s flash-ADC

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Abstract

This paper presents an online offset-cancellation method which is embedding in a low-power 6-bit flash analog to digital converter. A set of low-offset comparators are employed as the first step and then utilizing a novel online method leads to eliminate the effect of the relative offset between all comparators that is the origin of the bubble errors. The offset-cancellation mechanism is based on bulk-driven method where it takes about 0.7 µs for the bulk nodes to settle down and cancel the relative offset voltage. Simulation results using HSPICE software with standard 0.18 µm CMOS technology parameters, demonstrate 5.06 ENOB at 2 GS/s with the power consumption of 35 mW and 0.27 FoM.

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Authors and Affiliations

  1. Department of Microelectronics Engineering, Urumi Graduate Institute (UGI), Urmia, Iran

    Abdollah Amini, Ali Baradaranrezaeii & Mina Hassanzadazar

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  1. Abdollah Amini
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  2. Ali Baradaranrezaeii
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  3. Mina Hassanzadazar
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Correspondence to Abdollah Amini.

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Amini, A., Baradaranrezaeii, A. & Hassanzadazar, M. A novel online offset-cancellation mechanism in a low-power 6-bit 2GS/s flash-ADC. Analog Integr Circ Sig Process 99, 219–229 (2019). https://doi.org/10.1007/s10470-018-1375-2

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  • DOI: https://doi.org/10.1007/s10470-018-1375-2

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