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An ultra high-speed high-resolution low-offset low-power voltage comparator with a reliable offset cancellation method for high-performance applications in 0.18 µm CMOS technology

  • Mixed Signal Letter
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Abstract

In this paper a novel structure is presented as a voltage comparator, and a reliable offset cancellation technique is utilized as well. Moreover a comprehensive post layout simulation method is described to evaluate a vast verity of comparators in order to find out whether the designed structure will operate properly in the post fabrication (solid state) tests or not. A single stage architecture with a simple readout circuit leads to a low-offset low-power high-speed high-resolution comparator which qualifies for VLSI applications such as image sensors. Applying the reliable offset cancellation technique makes it qualified for high performance applications like high-speed high-resolution ADCs. The proposed comparator is simulated through the mentioned method in 0.18 µm standard CMOS technology, and 0.5 mV of accuracy in 1 G sample per second is obtained with a power consumption of 110 µW (150 µW with offset cancellation circuit) where an introduced offset of about 10 mV is cancelled to lower than 220 µV as well.

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Authors and Affiliations

  1. Microelectronics Research Laboratory, Urmia University, Urmia, Iran

    Ali Baradaranrezaeii, Obalit Shino, Khayrollah Hadidi & Abdollah Khoei

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  1. Ali Baradaranrezaeii
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  2. Obalit Shino
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  3. Khayrollah Hadidi
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  4. Abdollah Khoei
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Correspondence to Ali Baradaranrezaeii.

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Baradaranrezaeii, A., Shino, O., Hadidi, K. et al. An ultra high-speed high-resolution low-offset low-power voltage comparator with a reliable offset cancellation method for high-performance applications in 0.18 µm CMOS technology. Analog Integr Circ Sig Process 85, 181–192 (2015). https://doi.org/10.1007/s10470-015-0604-1

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  • DOI: https://doi.org/10.1007/s10470-015-0604-1

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