Abstract
In this paper, a 0.35 V, 82 pJ/conversion ring oscillator based ultra-low power CMOS all digital temperature sensor is presented for on-die thermal management. We utilize subthreshold circuit operation to reduce power and adopt an all-digital architecture, consisting of only standard digital gates. Additionally, a linearization technique is proposed to correct the nonlinear characteristics of subthreshold MOSFETs. A bulk-driven 1-bit gated digitally controlled oscillator is designed for the temperature sensing node. Also, a 1-bit time-to-digital converter is employed in order to double the fine effective resolution of the sensor. The proposed digital temperature sensor has been designed in a 90-nm regular V T CMOS process. After a two-point calibration, the sensor has a maximum error of −0.68 to +0.61 °C over the operating temperature range from 0 to 100 °C, while the effective resolution reaches 0.069 °C/LSB. Under a supply voltage of 0.35 V, the power dissipation is only 820 nW with the conversion rate of 10K samples/s at room temperature. Also, the sensor occupies a small area of 0.003 mm2.
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Huang, W., Ghosh, S., Velusamy, S., Sankaranarayanan, K., Skadron, K., & Stan, M. R. (2006). HotSpot: A compact thermal modeling methodology for early-stage VLSI design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(5), 501–513.
Pedram, M., & Nazarian, S. (2006). Thermal modeling, analysis, and management in VLSI circuits: Principles and methods. Proceedings of the IEEE, 94(8), 1487–1501.
Chen, D., Li, E., Rosenbaum, E., & Kang, S. M. (2000). Interconnect thermal modeling for accurate simulation of circuit timing and reliability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(2), 197–205.
Brooks, D., Dick, R. P., Joseph, R., & Li, S. (2007). Power, thermal, and reliability modeling in nanometer-scale microprocessors. IEEE Micro, 27(3), 49–62.
Ajami, A. H., Banerjee, K., Pedram, M., & van Ginneken, L. P. P. P. (2001). Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs. In Proceedings of IEEE/ACM Design Automation Conference (DAC) (pp. 567–572).
Liao, W., He, L., & Lepak, K. M. (2005). Temperature and supply voltage aware performance and power modeling at microarchitecture level. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(7), 1042–1053.
Black, J. R. (1969). Electromigration: A brief survey and some recent results. IEEE Transactions on Electron Devices, 16(4), 338–347.
Hu, C., Tam, S. C., Hsu, F. C., Ko, P. K., Chan, T. Y., & Terrill, K. W. (1985). Hot-electron-induced MOSFET degradation: Model, monitor, and improvement. IEEE Transactions on Electron Devices, 32(2), 375–385.
Chen, G., et al. (2003). Dynamic NBTI of PMOS transistors and its impact on device lifetime. In Proceedings of International Reliability Physics Symposium (pp. 196–202).
Huard, V., Denais, M., & Parthasarathy, C. (2006). NBTI degradation: From physical mechanisms to modelling. Microelectronics and Reliability, 46(1), 1–23.
Martin-Martinez, J., et al. (2007). Lifetime estimation of analog circuits from the electrical characteristics of stressed MOSFETs. Microelectronics Reliability, 47(9), 1349–1352.
Srinivasan, J., Adve, S. V., Bose, P., & Rivers, J. A. (2005). Lifetime reliability: Toward an architectural solution. IEEE Micro, 25(3), 70–80.
Gielen, G., et al. (2008). Emerging yield and reliability challenges in nanometer CMOS technologies. In Proceedings of the Design, Automation and Test in Europe (DATE) (pp. 1322–1327).
Brooks, D., & Martonosi, M. (2001). Dynamic thermal management for high-performance microprocessors. In Proceedings of International Symposium on High-Performance Computer Architecture (HPCA) (pp. 171–182).
Kumar, A., Li, S., Peh, L. S., & Jha, N. K. (2008). System-level dynamic thermal management for high-performance microprocessors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(1), 96–108 (2008).
Mitra, T., & Jayaseelan, R. (2009). Dynamic thermal management via architectural adaptation. In Proceedings of IEEE/ACM Design Automation Conference (DAC) (pp. 484–489).
Hameed, F., Faruque, M. A. A., & Henkel, J. (2011). Dynamic thermal management in 3D multi-core architecture through run-time adaptation. In Proceedings of the Design, Automation and Test in Europe (DATE) (pp. 299–304).
Ware M., et al. (2010). Architecting for power management: The IBM POWER7 approach. In Proceedings of International Symposium on High-Performance Computer Architecture (HPCA) (pp. 1–11).
Rotem, E., Hermerding, J., Cohen, A., & Cain, H. (2006). Temperature measurement in the Intel core duo processor. In Proceedings of International Workshop on Thermal Investigations of ICs (pp. 23–27).
Chen, P., Chen, C. C., Tsai, C. C., & Lu, W. F. (2005). A time-to-digital-converter-based CMOS smart temperature sensor. IEEE Journal on Solid-State Circuits, 40(8), 1642–1648.
Chen, P., Chen, T. K., Wang, Y. S., & Chen, C. C. (2009). A time-domain sub-micro watt temperature sensor with digital set-point programming. The IEEE Sensors Journal, 9(12), 1639–1646.
Chen, P., Chen, C. C., Peng, Y. H., Wang, K. M., & Wang, Y. S. (2010). A time-domain SAR smart temperature sensor with curvature compensation and a 3σ inaccuracy of −0.4°C ∼ +0.6°C over a 0°C to 90°C range. IEEE Journal on Solid-State Circuits, 45(3), 600–609.
Lin, Y. S., Sylvester, D., & Blaauw, D. (2008). An ultra low power 1 V, 220 nW temperature sensor for passive wireless applications. In Proceedings of IEEE Custom Integrated Circuits Conference (CICC) (pp. 507–510).
Kim, K., Lee, H., Jung, S., & Kim, C. (2009). A 366 kS/s 400 μW 0.0013 mm2 frequency-to-digital converter based CMOS temperature sensor utilizing multiphase clock. In Proceedings of IEEE Custom Integrated Circuits Conference (CICC) (pp. 203–206).
Lee, H., Kim, K., Jung, S., Song, J., Kim, J. K., & Kim, C. (2010). A 0.0018 mm2 frequency-to-digital-converter-based CMOS smart temperature sensor. Analog Integrated Circuits and Signal Processing, 62(2), 153–157.
Woo, K., Meninger, S., Xanthopoulos, T., Crain, E., Ha, D., & Ham, D. (2009). Dual-DLL-based CMOS all-digital temperature sensor for microprocessor thermal monitoring. In International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers (pp. 68–69).
Ituero, P., Ayala, J., & Lopez-Vallejo, M. (2008). A nanowatt smart temperature sensor for dynamic thermal management. IEEE Sensors Journal, 8(12), 2036–2043.
Park, S., Min, C., & Cho, S. H. (2009). A 95 nW ring oscillator-based temperature sensor for RFID tags in 0.13 μm CMOS. In International Symposium on Circuits and Systems (ISCAS) (pp. 1153–1156).
Morshed, T. H., et al. (2011). BSIM4v4.7 MOSFET Model (2011). http://www-device.eecs.berkeley.edu/bsim/Files/BSIM4/BSIM470/BSIM470_Manual.pdf. Accessed 24 Nov 2012.
Chen, P., Shie, M. C., Zheng, Z. Y., Zheng, Z. F., & Chu, C. Y. (2007). A fully digital time-domain smart temperature sensor realized with 140 FPGA logic elements. IEEE Transactions on Circuits and Systems I: Regular Papers, 54(12), 2661–2668.
Chen, P., Chen, S. C., Shen, Y. S., & Peng, Y. J. (2011). All-digital time-domain smart temperature sensor with an inter-batch inaccuracy of −0.7°C–+0.6°C after one-point calibration. IEEE Transactions on Circuits and Systems I: Regular Papers, 58(5), 913–920.
Chung, C. C., & Yang, C. R. (2011). An autocalibrated all-digital temperature sensor for on-chip thermal monitoring. IEEE Transactions on Circuits and Systems II: Express Briefs, 58(2), 105–109.
Lo, Y. L., Yang, W. B., Chao, T. S., & Cheng, K. H. (2009). Designing an ultralow-voltage phase-locked loop using a bulk-driven technique. IEEE Transactions on Circuits and Systems II: Express Briefs, 56(5), 339–343.
Cheng, K. H., Tsai, Y. C., Lo, Y. L., & Huang, J. S. (2011). A 0.5-V 0.4–2.24-GHz inductorless phase-locked loop in a system-on-chip. IEEE Transactions on Circuits and Systems I: Regular Papers, 58(5), 849–859.
Wismar, U., Wisland, D., & Andreani, P. (2007). Linearity of bulk-controlled inverter ring VCO in weak and strong inversion. Analog Integrated Circuits and Signal Processing, 50(1), 59–67.
Law, M., & Bermak, A. (2008). A time domain differential CMOS temperature sensor with reduced supply sensitivity. In International Symposium on Circuits and Systems (ISCAS) (pp. 2126–2129).
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Kim, Y., Li, P. A 0.003-mm2, 0.35-V, 82-pJ/conversion ultra-low power CMOS all digital temperature sensor for on-die thermal management. Analog Integr Circ Sig Process 75, 147–156 (2013). https://doi.org/10.1007/s10470-012-9988-3
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DOI: https://doi.org/10.1007/s10470-012-9988-3