Skip to main content
SpringerLink
Log in

A new approach to sizing analog CMOS building blocks using pre-compiled neural network models

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

There has been a constant endeavor towards improving the available circuit design automation tools to match technological advancements in the electronic industry. However, inadequate research efforts in the analog domain are holding back the exploitation of advanced technologies. A dearth of design expertise in the analog domain is the principal driving force for the growth of Design Automation (DA) tools. Transistor sizing is one of the most crucial steps in the analog IC design. In this paper, we put forward a new computer aided design framework for the sizing of transistors in MOS Integrated Circuit (IC) amplifiers by incorporating powerful modeling capabilities of Artificial Neural Networks (ANN). ANNs have proven to be efficient and accurate modeling tools in several applications. The proposed tool is capable of directly computing transistor related design parameters, of the MOS IC amplifier and associated peripheral circuitry. The proposed tool thus avoids several time-consuming simulations and/or tuning runs at the very bottom level of analog IC amplifier implementation, using a given CMOS process. It also reduces manual intervention in the design process, thus enhancing the automation of the design process. This paper presents design examples of several analog IC functional modules that are developed and verified successfully.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14

Similar content being viewed by others

References

  1. Toumazou, C., & Makris, C. A. (1995). Automated circuit generation: New concepts and methods. IEEE Transactions on Computer-Aided Design, 14, 218–238.

    Article  Google Scholar 

  2. Allen, P. E. (1986). A tutorial-computer aided design of analog integrated circuits. In IEEE proceedings of the custom integrated circuits conference (CICC) (pp. 608–616). Rochester, NY, May 1986.

  3. Cohn, J. M., Garrod, D. J., Rutenbar, R. A., & Carley, R. (1994). Analog device-level layout automation. New York, NY: Springer.

    Book  MATH  Google Scholar 

  4. Gajski, D. D., Dutt, N. D., & Pangrale, B. M. (1986). Silicon compilation (tutorial). In IEEE Proceedings of CICC (pp. 102–110). Rochester, NY, May 1986.

  5. Massara, R. E., Nadiadi, Y., & Winder, G. L. (1989). Silicon compilation in analog and digital custom VLSI design. In Progress in computer aided VLSI design (pp. 91–135). Ablex: New York, NY.

  6. Smith, M. J. S., Portmann, C., Anagnostopoulos, C., Tschang, P. S., Rao, R., Valdenaire, P., et al. (1989). Cell libraries and assembly tools for analog/digital CMOS & BiCMOS application-specific integrated circuit design. IEEE Journal of Solid-State Circuits, 24, 1419–1432.

    Article  Google Scholar 

  7. Raut, R. (2002). Introduction to analog VLSI—lecture notes. Montreal, QC: Concordia University Publication.

    Google Scholar 

  8. Johns, D., & Martin, K. (1997). Analog integrated circuit design. New York, NY: Wiley.

    Google Scholar 

  9. El-Turky, F., & Perry, E. E. (1989). BLADES: An artificial intelligence approach to analog circuit design. IEEE Transactions on Computer-Aided Design, 8, 680–692.

    Article  Google Scholar 

  10. Harjani, R., Rutenbar, R. A., & Carley, L. R. (1989). OASYS: A framework for analog circuit synthesis. IEEE Transactions on Computer-Aided Design, 8, 1247–1266.

    Article  Google Scholar 

  11. Berkcan, E., & Yassa, F. (1990). Towards mixed analog/digital design automation: A review. In IEEE international symposium on circuits systems. New Orleans, LA, May 1990.

  12. Degrauwe, M. G. R., Nys, O., Dijkstra, E., Rijmenants, J., Bitz, S., Goffart, B. L. A. G., et al. (1987). IDAC: An interactive design tool for analog CMOS circuits. IEEE Journal of Solid-State Circuits, 22, 1106–1116.

    Article  Google Scholar 

  13. Degrauwe, M., Goffart, B., Meixenberger, C., Pierre, M., Litsios, J., Rijmenants, J., et al. (1989). Towards an analog system design environment. IEEE Journal of Solid-State Circuits, 24, 659–671.

    Article  Google Scholar 

  14. Koh, H. Y., Sequin, C. H., & Gray, P. R. (1990). OPASYN: A compiler for CMOS operational amplifiers. IEEE Transactions on. Computer-Aided Design, 9, 113–125.

    Article  Google Scholar 

  15. Gielen, G. G. E., Walscharts, H. C. C., & Sansen, W. M. C. (1990). “Analog circuit design optimization based on symbolic simulation and simulated annealing”. IEEE J. Solid-State Circuits, 25, 707–713.

    Article  Google Scholar 

  16. Onodera, H., Kanbara, H., & Tamaru, K. (1990). “Operational-amplifier compilation with performance optimization”. IEEE J. Solid-State Circuits, 25, 466–473.

    Article  Google Scholar 

  17. Ressler, A. L. (1984). A circuit grammar for operational amplifier design. Ph.D. dissertation, MIT.

  18. Nye, W., Riley, D. C., Sangiovanni-Vincentelli, A., & Tits, A. L. (1988). DELIGHT.SPICE: An optimization-based system for the design of integrated circuits. IEEE Transactions on Computer-Aided Design, 7, 501–519.

    Article  Google Scholar 

  19. Shyu, J., & Sangiovanni-Vincentelli, A. (1988). ECSTASY: A new environment for IC design optimization. In: IEEE international conference on computer-aided design (ICCAD) (pp. 484–487). San Jose, CA, Nov. 1988.

  20. Lai, J. C., Kueng, J. S., Chen, H. C., & Fernandez, F. J. (1988). ADOPT-A CAD tool for analog circuit design. IEEE Circuits and Devices Magazine, 4, 29–30.

    Article  Google Scholar 

  21. Medeiro, F., Pérez-Verdú, B., & Rodríguez-Vázquez, A. (1998). Top-down design of high-performance sigma-delta modulators. Boston, USA: Kluwer Academic Publishers. ISBN 0-7923-8352-4.

  22. Ruiz-Amaya, J., de la Rosa, J. M., Fernández, F. V., Medeiro, F., del Río, R., Pérez-Verdú, B., & Rodríguez-Vázquez, A. (2005). High-Level synthesis of switched-Capacitor, switched-Current and continuous-time SD modulators using SIMULINK-based time-domain behavioral models. In IEEE transactions on circuits and systems-I (Vol. 52, pp. 1795–1810), IEEE September 2005.

  23. Barros, M. F. M., Guilherme, J. M. C., & Horta, N. C. G. (2010). Analog circuits and systems optimization based on evolutionary techniques. Berlin: Springer.

    Book  MATH  Google Scholar 

  24. Sommer, R., Hennig, E., Thole, M., Halfmann, T., & Wichmann, T. (2000). Analog Insydes 2—new features and applications in circuit design. In International workshop on symbolic methods and applications in circuit design (SMACD). Lisbon, Portugal.

  25. Fernández, F.V., Rodríguez-Vázquez, A., Huertas, J. L., & Gielen, G. (1998). Symbolic analysis techniques: Applications to analog design automation. Piscataway, NJ: IEEE Press.

  26. Fakhfakh, M., Tlelo-Cuautle, E., & Fernandez, F. V. (Eds.). (2010). Design of analog circuits through symbolic analysis. United Arab Emirates: Bentham scientific publisher.

    Google Scholar 

  27. Daems, W., Gielen, G., & Sansen, W. (2003). Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits. IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, 22, 517–534.

    Article  Google Scholar 

  28. Leyn, F., Gielen, G., & Sansen, W. (1998). An efficient dc root solving algorithm with guaranteed convergence for analog integrated cmos circuits. In Proceedings of IEEE/ACM international conference on computer-aided design (pp. 304–307), Nov. 1998.

  29. Tomohiro, F., & Osamu, I. (2006). Analog circuit sizing with dynamic search window. In IEEE international symposium on circuits and systems (pp. 2945–2948). Island of Kos, Greece, May 2006.

  30. Han, D., & Chatterjee, A. (2004). Simulation-in-the-loop Analog Circuit Sizing Method using Adaptive Model-based Simulated Annealing. In IEEE international workshop on system-on-chip for real-time applications (pp. 127–130). Banff, Alberta, Canada, July 2004.

  31. Kahraman, N., & Yildirim, T. (2008). Technology independent fundamental circuit sizing for analog circuits using Artificial Neural Networks. Research in Microelectronics and Electronics, PRIME (pp. 1–4). Istanbul, Turkey, June 2008.

  32. Kahramana, N., & Yildirim, T. (2009). Technology independent circuit sizing for standard cell based design using neural networks. Digital Signal Processing, 19(4), 708–714.

    Google Scholar 

  33. Andreev, N., Kazakov, V. A., & Svetlov, A. V. (1999). A Macromodel of an OPAMP for modeling measurement circuits with pulsed signal. Measurement Technology, 42(9), 858–863.

    Article  Google Scholar 

  34. Alpaydin, G., Balkir, S., & Dundar, G. (2003). An evolutionary approach to automatic synthesis of high-performance analog integrated circuits. IEEE Transactions on Evolutionary Computation, 7(3), 240–252.

    Article  Google Scholar 

  35. Balkir, S., Dundar, G., & Alpaydin, G. (2004). Evolution based synthesis of analog integrated circuits and systems. In NASA/DoD conference on evolvable hardware (pp. 26–29). Seattle, WA, June 2004.

  36. Mendhurwar, K. A., Devabhaktuni, V. K., & Raut, R. (2008). Binning algorithm for accurate computer aided device modeling. In IEEE international symposium on circuits systems (pp. 2773–2776). Seattle, WA, May 2008.

  37. Mendhurwar, K. A., Devabhaktuni, V. K., & Raut, R. (2008). A new computer- aided multi-dimensional device modeling algorithm based on binning concepts. In IEEE international conference on microelectronics (pp. 477–480). Nis, Serbia, May 2008.

  38. Mendhurwar, K. A., Bhattacharya, P. B., Devabhaktuni, V. K., & Raut, R. (2009). A new neural network modeling approach based on a correction model concept. In IEEE conference on microwave Asia-Pacific (pp. 1497–1500). Singapore, Singapore, Dec. 2009.

  39. Mendhurwar, K. A., Sundani, H., Khan, Z., Bhattacharya, P., & Devabhaktuni, V. (2009). Device modeling using correction model based ANN and support vector regression. In 12th international symposium on microwave and optical technology. New Delhi, India, Dec. 2009.

  40. Zhang, Q. J., Gupta, K. C., & Devabhaktuni, V. K. (2003). Artificial neural networks for RF and microwave design–From theory to practice. IEEE Transactions on Microwave Theory and Techniques, 51, 1339–1350.

    Article  Google Scholar 

  41. Devabhaktuni, V. K., Yagoub, M. C. E., Fang, Y., Xu, J., & Zhang, Q. J. (2001). Neural networks for microwave modeling: Model development issues and nonlinear modeling techniques. International Journal of RF and Microwave Computer-Aided Engineering, 11, 4–21.

    Article  Google Scholar 

  42. Ding, X., Devabhaktuni, V. K., Chattaraj, B., Yagoub, M. C. E., Deo, M., Xu, J., et al. (2004). Neural-network approaches to electromagnetic-based modeling of passive components and their applications to high-frequency and high-speed nonlinear circuit optimization. IEEE Transactions on Microwave Theory and Techniques, 52, 436–449.

    Article  Google Scholar 

  43. Devabhaktuni, V. K., Chattaraj, B., Yagoub, M. C. E., & Zhang, Q. J. (2003). Advanced microwave modeling framework exploiting automatic model generation, knowledge neural networks, and space mapping. IEEE Transactions on Microwave Theory and Techniques, 51, 1822–1833.

    Article  Google Scholar 

  44. Watson, P. M., Gupta, K. C., & Mahajan, R. L. (1998). Development of knowledge based artificial neural network models for microwave components. In Proceedings of the IEEE international microwave symposium (pp. 9–12). Baltimore, MD, June 1998.

  45. Haykin, S. (1998). Neural Networks: A comprehensive foundation. (2nd ed.). New Jersey: Prentice Hall.

  46. Abou-Allam, E., & Manku, T. (1997). A small-signal MOSFET model for radio frequency IC applications. IEEE Transactions on Computer-Aided Design, 16, 437–447.

    Article  Google Scholar 

  47. Zeki, A., & Kuntman, H. (1997). Accurate and high output impedance current mirror suitable for CMOS current output stages. Electronics Letters, 33, 1042–1043.

    Google Scholar 

  48. Sackinger, E., & Guggenbuhl, W. (1990). A high swing, high impedance MOS cascode circuit. IEEE Journal of Solid-State Circuits, 25, 289–297.

    Google Scholar 

  49. Baker, R. J., Li, H. W., & Boyce, D. E. (1998). CMOS circuit design, layout, and simulation. New York, NY: IEEE Press.

    Google Scholar 

  50. Allen, P. E., & Holberg, D. R. (2002). CMOS analog circuit design. New York, NY: Oxford University Press.

    Google Scholar 

  51. Razavi, B. (2001). Design of analog CMOS integrated circuits. New York, NY: McGraw-Hill.

    Google Scholar 

  52. Antao, B. A. A. (1996). Trends in CAD of analog ICs. IEEE Circuits and Devices Magazine, 12, 31–41.

    Article  Google Scholar 

  53. Tsividis, Y. P. (1987). Analog MOS integrated circuits-certain new ideas, trends, and obstacles. IEEE Journal of Solid-State Circuits, 22(3), 317–321.

    Article  Google Scholar 

  54. Zhang, Q. J. (1999). NeuroModeler. Ottawa: Department of Electronics, Carleton University.

  55. Tarassenko, I., & Roberts, S. (1994). Supervised and unsupervised learning in radial basis function classifiers. IEEE Proceedings-Vision, Image and Signal Processing, 141, 210–216.

    Google Scholar 

  56. Bishop, C. M. (1991). Improving the generalization properties of radial basis function neural networks. Neural Computation, 3(4), 579–588.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of ECE, Concordia University, 1455 de Maisonneuve W, Montreal, QC, H3G 1M8, Canada

    Kaustubha Mendhurwar & Rabin Raut

  2. EECS Department, MS 308, University of Toledo, 2801 W. Bancroft St., Toledo, OH, 43606, USA

    Harsh Sundani, Priyanka Aggarwal & Vijay Devabhaktuni

Authors
  1. Kaustubha Mendhurwar
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Harsh Sundani
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Priyanka Aggarwal
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Rabin Raut
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Vijay Devabhaktuni
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Vijay Devabhaktuni.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Mendhurwar, K., Sundani, H., Aggarwal, P. et al. A new approach to sizing analog CMOS building blocks using pre-compiled neural network models. Analog Integr Circ Sig Process 70, 265–281 (2012). https://doi.org/10.1007/s10470-011-9648-z

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-011-9648-z

Keywords

Search

Navigation