Abstract
Recent high-density very large scale integrated (VLSI) interconnections in multichip modules require high-reliability solder interconnection to enable us to achieve small interconnect size andlarge number of input/output terminals, and to minimize soft errors in VLSIs induced by α-particle emission from solder. Lead-free solders such as indium (In)-alloy solders are a possible alternative to conventional lead-tin (Pb-Sn) solders. To realize reliable interconnections using In-alloy solders, fatigue behavior, finite element method (FEM) simulations, and dissolution and reaction between solder and metallization were studied with flip-chip interconnection models. We measured the fatigue life of solder joints and the mechanical properties of solders, and compared the results with a computer simulation based on the FEM. Indium-alloy solders have better mechanical properties for solder joints, and their flip-chip interconnection models showed a longer fatigue life than that of Pb-Sn solder in thermal shock tests between liquid nitrogen and room temperatures. The fatigue characteristics obtained by experiment agree with that given by FEM analysis. Dissolution tests show that Pt film is resistant to dissolution into In solder, indicating that Pt is an adequate barrier layer material for In solder. This test also shows that Au dissolution into the In-Sn solder raises its melting point; however, Ag addition to In-Sn solder prevents melting point rise. Experimental results show that In-alloy solders are suitable for fabricating reliable interconnections.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
K. Seelig et al.,Proc. NEPCON East ’87, June 1987, p. 3.
R. Keeler,Electron. Packaging < Production July (1987), p. 45.
L.S. Goldmann et al.,Parts, Hybrids, and Packaging No.3, (1977), p. 194.
R.T. Howard,IBM J. Res. Develop. 26, (3) 372 (1982).
N. Honma et al.,IEICE Trans. E74, (8) (1980).
K.C. Norris and A.H. Landzberg,IBMJ. Res. Develop. 13, 266 (1969).
L.S. Goldmann,IBMJ. Res. Develop. 13, 251 (1969).
K. Hashimoto, T. Yamada, T. Sato, and K. Niwa, presented at the 1988 IEEE VLSI and GaAs Chip Packaging Workshop, Santa Clara, CA, Sept. 12–14, 1988.
F.H. Gaensslen, Proc.IEEE 1980 Int. Conf. Circuits and Computers I, (1980), p. 450.
T. Mimura et al.,Jpn. J. Appl. Phys. 19, (5) L225 (1980).
T. Mimura et al.,Jpn. J. Appl. Phys. 20, (8) L598 (1981).
R.R. Tummala and E.J. Rymaszewski,Microelectronics Packaging Handbook, (New York: Van Nostrand Reinhold, 1989), p. 378.
R.N. Wild,Proc. NEPCON (1974), p. 105.
R. Satoh, K. Arakawa, M. Harada and K. Matsui,IEEE Trans. Comp. Hybrids and Manufacturing Technology, 14, (1) 224, (March 1991).
ABAQUS,User’s Manual Version 5.2, Vol.1,2, (Pawtucket: Hibbitt, Karlsson < Sorensen, Inc., 1993).
K. Karasawa, T. Nakanishi, M. Ochiai and K. Hashimoto,Proc. 1992 IMC, June (1992), p. 136.
K. Hashimoto, E. Horikoshi, T. Sato and K. Niwa, Z. Henmi,IEEE Trans. CHMT, vol. CHMT-8, No.4, (December 1985), p. 541.
M. Hansen and K. Anderko,Constitution of Binary Alloys, (New York: McGraw-Hill Book Company, Inc., 1958).
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Shimizu, K., Nakanishi, T., Karasawa, K. et al. Solder joint reliability of indium-alloy interconnection. J. Electron. Mater. 24, 39–45 (1995). https://doi.org/10.1007/BF02659725
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF02659725