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Testability-based partial scan analysis

  • Testability Analysis Based Algorithms
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Abstract

In this paper, we present a new method for selecting flip-flops for partial scan. Our method ranks all flip-flops in a circuit based on a sensitivity analysis which estimates the relative improvement in the testability of the circuit as a result of scanning a flip-flop. The testability is an estimate of the fault coverage expected for the circuit and is computed with respect to a given set of target faults. Several cost functions are used to compute testability, taking both structural and logical aspects of the circuit into account. Our results show a good correlation between the computed testability and the actual fault coverage. We give a testability-based estimate on the number of scan flip-flops needed to reach a high fault coverage.

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Authors and Affiliations

  1. AT&T, 2000 N. Naperville Rd., Room: IL0015 5A411, 60566, Naperville, IL

    Prashant S. Parikh

  2. AT&T Bell Laboratories, 600 Mountain Ave., Room: NJ9620 2AZ36, 07974, Murray Hill, NJ

    Miron Abramovici

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  1. Prashant S. Parikh
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  2. Miron Abramovici
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Parikh, P.S., Abramovici, M. Testability-based partial scan analysis. J Electron Test 7, 61–70 (1995). https://doi.org/10.1007/BF00993314

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  • DOI: https://doi.org/10.1007/BF00993314

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