Skip to main content
SpringerLink
Log in

I DDQ testing: A review

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Quiescent power supply current (I DDQ ) testing of CMOS integrated circuits is a technique for production quality and reliability improvement, design validation, and failure analysis. It has been used for many years by a few companies and is now receiving wider acceptance as an industry tool. This article begins with a brief history of CMOS ICs to provide perspective on the origin of I DDQ testing. Next, the use of I DDQ testing for IC quality improvement through increased defect and fault detection is described. Then implementation issues are considered, including test pattern generation software, hardware instrumentation, limit setting, IC design guidelines, and defect diagnosis. An extended reference list is provided to help the reader obtain more information on specific aspects.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. F.M. Wanlass and C.T. Sah, “Nanowatt logic using field-effect metal-oxide semiconductor triodes,” Proc. Solid State Circuits Conf., pp. 32–33, February 1963.

  2. M.J. Riezenman, “Wanlass's CMOS circuit,” IEEE Spectrum, p. 44, May 1991.

  3. EE Times, Issue 503A, September 1988.

  4. R.N. Noyce and M.E. Hoff, Jr., “A history of microprocessor development at Intel,” IEEE Micro, pp. 8–21, February 1991.

  5. User Manual, CDP1802 COSMAC Microprocessor, RCA Corporation, November 1977.

  6. J. Flood, “Fundamentals of testing COS/MOS integrated circuits,” RCA Solid-State Integrated Circuits Databook, Application Note ICAN-6532, pp. 622–630, 1978.

  7. R.G. Daniels, “The changing demands of microprocessor testing,” Keynote address, Proc. Int. Test Conf., September 1990.

  8. G.F. Nelson and W.F. Boggs, “Parametric tests meet the challenge of high-density ICs,” Electronics, pp. 108–111, December 11, 1975.

  9. G.F. Nelson; personal communications, March 1988.

  10. W.J. Barnard, G.W. Garrett, and L.K. Horning; personal communication, August 1992.

  11. C.F. Hawkins and J.M. Soden, “Electrical characteristics and testing considerations for gate oxide shorts in CMOS ICs,” Proc. Int. Test Conf., pp. 544–555, November 1985.

  12. C.F. Hawkins, J.M. Soden, R.R. Fritzemeier, and L.K. Horning, “Quiescent power supply current measurement for CMOS IC defect detection,” IEEE Trans. on Indus. Electron., vol. 36, no. 2, pp. 211–218, May 1989.

    Google Scholar 

  13. M. Levi, “CMOS is most testable,” Proc. Int. Test Conf., pp. 217–220, October 1981.

  14. Y.K. Malaiya and S.Y.H. Su, “A new fault model and testing technique for CMOS devices,” Proc. Int. Test Conf., pp. 25–34, November 1982.

  15. R.R. Fritzemeier, J.M. Soden, K.R. Treece, and C.F. Hawkins, “Increased CMOS IC stuck-at fault coverage with reduced I DDQ test sets,” Proc. Int. Test Conf., pp. 427–435, September 1990.

  16. W. Mao, R.K. Gulati, D.K. Goel, and M. Ciletti, “QUIETEST: A quiescent current testing methodology for detecting leakage faults,” Proc. ICCAD, pp. 280–283, November 1990.

  17. R.J. Perry, “I DDQ testing in CMOS digital ASIC's—putting it all together,” Proc. Int. Test Conf., pp. 151–157, September 1992.

  18. R.J. Perry, “I DDQ testing in CMOS digital ASIC's,” J. of Electronic Testing: Theory and Applications (JETTA), vol. 3, no. 4, pp. 317–325, December 1992.

    Google Scholar 

  19. S.D. McEuen, “IDDq benefits,” Proc. IEEE VLSI Test Symp., pp. 285–290, April 1991.

  20. S.D. McEuen, “Reliability benefits of I DDQ ,” J. of Electronic Testing: Theory and Applications (JETTA), vol. 3, no. 4, pp. 328–335, December 1992.

    Google Scholar 

  21. T. Frederiksen, Intuitive IC CMOS Evolution, Donnelley Press, 1984.

  22. J.M. Soden and C.F. Hawkins, “Electrical properties and detection methods for CMOS IC defects,” Proc. 1st European Test Conf., pp. 159–167, April 1989.

  23. C.T. Wang, “Voltage-current characteristic model for gate-oxide short induced standby current failures in CMOS ICs,” Proc. Electrical Overstress/Electrostatic Discharge Symp., pp. 246–251, September 1987.

  24. D.J. Burns, “Locating high resistance shorts in CMOS circuits by analyzing supply current measurement vectors,” Proc. Inter. Symp. for Testing and Failure Analysis, pp. 231–237, November 1989.

  25. R.C. Aitken, “Fault location with current monitoring,” Proc. Int. Test Conf., pp. 623–632, October 1991.

  26. R.C. Aitken, “A comparison of defect models for fault location with current monitoring,” Proc. Int. Test Conf., pp. 778–787, September 1992.

  27. R.C. Aitken, “Diagnosis of leakage faults with I DDQ ,” J. of Electronic Testing: Theory and Applications (JETTA), vol. 3, no. 4, pp. 363–375, December 1992.

    Google Scholar 

  28. R. Bottini, D. Calvi, S. Gaviraghi, A. Haardt, D. Turrini, and M. Vanzi, “Failure analysis of CMOS devices with anomalous IDD currents,” Int. Symp. for Testing and Failure Analysis (ISTFA), pp. 381–388, November 1991.

  29. C.F. Hawkins, J.M. Soden, E.I. Cole Jr., and E.S. Snyder, “The use of light emission in failure analysis of CMOS ICs,” Int. Symp. for Testing and Failure Analysis (ISTFA), pp. 55–67, October 29–November 2, 1990.

  30. R. Rodriguez-Montanes, E. Bruls, and J. Figueras, “Bridging defects resistance measurements in a CMOS process,” Proc. Int. Test Conf., pp. 892–899, September 1992.

  31. J.M. Acken, “Deriving accurate fault models,” Ph.D. thesis, Technical Report No. CSL-TR-88–365, Stanford University, CA, October 1988.

    Google Scholar 

  32. W. Yarbrough, “A testing methodology and test chip design strategy for IC fabrication process assessment, problem diagnosis, and yield analysis,” Ph.D. thesis, Stanford University, Stanford, CA, April 1988.

    Google Scholar 

  33. H. Hao and E.J. McCluskey, “On the modeling and testing of gate oxide shorts in CMOS logic gates,” IEEE Intl. Workshop on Defect and Fault Tolerance in VLSI Systems, Hidden Valley, PA, November 1991.

  34. T. Guckert, P. Schani, M. Phillips, M. Seeley, and N. Herr, “Design and process issues for elimination of device failures due to ‘drooping’ vias,” Proc. Int. Symp. for Testing and Failure Analysis (ISTFA), pp. 97–101, November 1991.

  35. C.F. Hawkins and J.M. Soden, “Reliability and electrical properties of gate oxide shorts in CMOS ICs,” Proc. Int. Test Conf., pp. 443–451, September 1986.

  36. H. Hao and E.J. McCluskey, “Resistive shorts within CMOS gates,” Proc. Int. Test Conf., pp. 292–301, October 1991.

  37. J.A. Segura, V.H. Champac, R. Rodrigues-Montanes, J. Figueras, and J.A. Rubio, “Quiescent current analysis and experimentation of defective CMOS circuits,” J. of Electronic Testing: Theory and Applications (JETTA), vol. 3, no. 4, pp. 337–348, December 1992.

    Google Scholar 

  38. A.N. Campbell, E.I. Cole, C.L. Henderson, and M.R. Taylor, “Case history: failure analysis of a CMOS SRAM with an intermittent open contact,” Proc. Int. Symp. for Testing and Failure Analysis (ISTFA), pp. 261–269, November 1991.

  39. C.L. Henderson, J.M. Soden, and C.F. Hawkins, “The behavior and testing implications of CMOS IC logic gate open circuits,” Proc. Int. Test Conf., pp. 302–310, October 1991.

  40. J.M. Soden and C.F. Hawkins, “Reliability of CMOS ICs with gate oxide shorts,” Semiconductor Int., pp. 240–245, May 1987.

  41. C.W. Green, “PMOS dynamic RAM reliability—a case study,” Proc. Int. Reliability Physics Symp, pp. 213–219, April 1979.

  42. J.A. Abraham, “VLSI Testing,” Chapter 1. Fault Modeling in VLSI, Amsterdam: North-Holland, Elsevier Science Publishers, pp. 1–27, 1986.

    Google Scholar 

  43. S. Gai, M. Mezzalama, and P. Prinetto, “A review of fault models for LSI/VLSI devices,” Software & Microsystems, vol. 2, pp. 44–53, April 1983.

    Google Scholar 

  44. S.D. Millman and J.P. Garvey, “An accurate bridging fault test pattern generator,” Proc. Int. Test Conf., pp. 411–418, October 1991.

  45. R.L. Wadsack, “Fault modeling and logic simulation of CMOS and MOS integrated circuits,” Bell Systems Tech. J., vol. 57, pp. 1449–1448, May–June 1978.

    Google Scholar 

  46. J.M. Soden, R.K. Treece, M.R. Taylor, and C.F. Hawkins, “CMOS IC stuck-open fault electrical effects and design considerations,” Proc. Int. Test Conf., pp. 423–430, August 1989.

  47. F.J. Ferguson and J.P. Shen, “Extraction and simulation of realistic CMOS faults using inductive fault analysis,” Proc. Int. Test Conf. pp. 475–484, September 1988.

  48. R.R. Fritzemeier, C.F. Hawkins, and J.M. Soden, “CMOS IC fault models, physical defect coverage, and I DDQ testing,” Proc. Custom Integ. Circuits Conf. (CICC), pp. 13.1.1–13.1.8, May 1991.

  49. P.M. Maxwell, R.C. Aitken, V. Johansen, and I. Chiang, “The effectiveness of I DDQ , functional, and scan tests: how many fault coverages do we need,” Proc. Int. Test Conf., pp. 168–177, September 1992.

  50. P.M. Maxwell and R.C. Aitken, “I DDQ testing as a component of a test suite: the need for several fault coverages,” J. of Electronic Testing: Theory and Applications (JETTA), vol. 3, no. 4, pp. 305–316, December 1992.

    Google Scholar 

  51. T. Storey, W. Maly, J. Andrews, and M. Miske, “Stuck fault and current testing comparison using CMOS chip test,” Int. Test Conf., pp. 311–318, October 1991.

  52. M. Renovell and G. Cambon, “Topology dependence of floating gate faults in MOS circuits,” Electr. Letters, vol. 22, pp. 152–153, January 1986.

    Google Scholar 

  53. W. Maly, P.K. Nag, and P. Nigh, “Testing oriented analysis of CMOS ICs with opens,” Proc. Int. Conf. Comp. Aid. Design (ICCAD), pp. 344–347, November 1988.

  54. J.M. Acken, “Testing for bridging faults (shorts) in CMOS circuits,” Des. Auto. Conf., pp. 717–718, June 1983.

  55. T. Storey and W. Maly, “CMOS bridging fault detecting,” Proc. Int. Test Conf., pp. 842–851, September 1990.

  56. M. Jacomino, J.L. Rainard, and R. David, “Fault detection by consumption measurement in CMOS circuits,” Proc. 3rd Int. Conf on Fault Tol. Comput. Sys., pp. 83–94, F. Belli and W. Dorke (ed.), Berlin: Springer-Verlag, 1987.

    Google Scholar 

  57. W. Mao and R.K. Gulati, “QUIETEST: a methodology for selecting I DDQ test vectors,” J. Electronic Testing: Theory and Applications (JETTA), vol. 3, no. 4, pp. 349–357, December 1992.

    Google Scholar 

  58. J.M. Soden, R.R. Fritzemeier, and C.F. Hawkins, “Zero defects or zero stuck-at faults—CMOS IC process improvement with I DDQ ,” Int. Test Conf., pp. 255–256, September 1990.

  59. J.L. Carter, V.S. Iyengar, and B.K. Rosen, “Efficient test coverage for delay faults,” Proc. Int. Test Conf., pp. 418–427, September 1987.

  60. K. Sawada and S. Kayano, “An evaluation of I DDQ versus conventional testing for CMOS sea-of-gate ICs,” Proc. Int. Test Conf., pp. 158–167, September 1992.

  61. R.K. Gulati, W. Mao, and D.K. Goel, “Detection of ‘undetectable’ faults using I DDQ testing,” Proc. Int. Test Conf., pp. 770–777, September 1992.

  62. E. Vandris and G. Sobelman, “A mixed functional/I DDQ testing methodology for CMOS transistor faults,” Proc. Int. Test Conf., pp. 608–614, October 1991.

  63. S.W. Bollinger and S.F. Midkiff, “On test generation for I DDQ of bridging faults,” Proc. Int. Test Conf., pp. 598–607, October 1991.

  64. C.H. Chen and J.A. Abraham, “High quality tests for switch-level circuits using current and logic generation algorithms,” Proc. Int. Test Conf., pp. 615–622, October 1991.

  65. C.H. Chen and J.A. Abraham, “Generation and evaluation of current and logic tests for switch-level sequential circuits,” J. of Electronic Testing: Theory and Applications (JETTA), vol. 3, no. 4, pp. 359–366, December 1992.

    Google Scholar 

  66. M. Keating and D. Meyer, “A new approach to dynamic IDD testing,” Proc. Inter. Test Conf., pp. 316–321, September 1987.

  67. K.M. Wallquist, A.W. Righter, and C.F. Hawkins, “Implementation of a voltage decay method for I DDQ measurement on the HP82000,” Hewlett-Packard User Group Mtg., San Francisco, CA, June 1992.

  68. C. Crapuchettes, “Testing CMOS IDD on large devices,” Proc. Inter. Test Conf., pp. 310–315, September 1987.

  69. D. Feltham, P. Nigh, L.R. Carley, and W. Maly, “Current sensing for built-in testing of CMOS circuits,” Proc. Int. Conf. on Computer Des., pp. 454–457, Rye Brook, NY, October 1988.

  70. W. Maly and M. Patyra, “Built-in current testing,” IEEE Trans. on Solid State Ckts., vol. 27, pp. 425–428, March 1992.

    Google Scholar 

  71. Y. Miura and K. Kinoshita, “Circuit design for built-in current testing,” Proc. Int. Test Conf., pp. 873–881, September 1992.

  72. J. Rius and J. Figueras, “Proportional testing for current testing,” J. Electronic Testing: Theory and Applications (JETTA), vol. 3, no. 4, pp. 387–396, December 1992.

    Google Scholar 

  73. A. Welbers, B. Verhelst, E. Seevinck, and K. Baker, “A built-in CMOS Idd quiescent monitor circuit,” Philips internal report, 1989.

  74. W. Maly and M. Patyra, “Design of ICs applying built-in current testing,” J. of Electronic Testing: Theory and Applications (JETTA), vol. 3, no. 4, pp. 397–406, December 1992.

    Google Scholar 

  75. L.K. Horning, J.M. Soden, R.R. Fritzemeier, and C.F. Hawkins, “Measurements of quiescent power supply current for CMOS ICs in production testing,” Proc. Int. Test Conf., pp. 300–309, September 1987.

  76. S. Chakravarty and M. Liu, “Algorithms for I DDQ measurement based diagnosis of bridging faults,” J. of Electronic Testing: Theory and Applications (JETTA), vol. 3, no. 4, pp. 337–385, December 1992.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department 2275, Sandia National Laboratories, PO Box 5800, 87185-5800, Albuquerque, NM, USA

    Jerry M. Soden

  2. Electrical and Computer Engr. Dept., The University of New Mexico, 87131, Albuquerque, NM, USA

    Charles F. Hawkins

  3. Ford Microelectronics, Inc., 9965 Federal Drive, 80921-3698, Colorado Springs, CO, USA

    Ravi K. Gulati & Weiwei Mao

Authors
  1. Jerry M. Soden
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Charles F. Hawkins
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Ravi K. Gulati
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Weiwei Mao
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Soden, J.M., Hawkins, C.F., Gulati, R.K. et al. I DDQ testing: A review. J Electron Test 3, 291–303 (1992). https://doi.org/10.1007/BF00135333

Download citation

  • Received:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF00135333

Keywords

Search

Navigation