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Ordered Binary Decision Diagrams

Foundations, Applications and Innovations

  • Chapter
Logic Synthesis and Verification

Part of the book series: The Springer International Series in Engineering and Computer Science ((SECS,volume 654))

Abstract

Ordered Binary Decision Diagrams (OBDDs) play a key role in the automated synthesis and formal verification of digital systems. They are the state-of-the-art data structure for representing switching functions in various branches of electronic design automation. In the following we discuss the properties of this data structure, characterize its algorithmic behavior, and describe some prominent applications.

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References

  1. S. B. Akers, “Binary decision diagrams”, IEEE Trans. on Computers, No. 27, pp. 509–516. 1978.

    Article  MATH  Google Scholar 

  2. R. I. Bahar, E. A. Frohm, C. M. Gaona, G. D. Hachtel, E. Machi, A. Pardo, F. Somenzi, “Algebraic decision diagrams and their application”, Proc. IEEE International Conference on Computer-Aided Design, (Santa Clara, CA), pp. 188–191, 1993.

    Google Scholar 

  3. J. Bern, Ch. Meinel, A. Slobodová, “OBDD-based Boolean manipulation in CAD beyond current limits”, Proc. 32nd ACM/IEEE Design Automation Conference, (San Francisco, CA), pp. 408–413, 1995.

    Google Scholar 

  4. B. Bollig, I. Wegener, “Improving the variable ordering of OBDDs is NP-complete”, IEEE Transactions on Computers, No. 45, pp. 993–1002, 1996.

    Article  MATH  Google Scholar 

  5. R. E. Bryant, “Graph-based algorithms for Boolean function manipulation”, IEEE Transactions on Computers, C–35, pp. 677–691, 1986.

    Article  Google Scholar 

  6. R. E. Bryant, “On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication”, IEEE Transactions on Computers, C–40, pp. 205–213, 1991.

    Article  Google Scholar 

  7. R. E. Bryant, “Symbolic Boolean manipulation with ordered binary decision diagrams”, ACM Computing Surveys, No. 24(3), pp. 293–318, 1992.

    Article  Google Scholar 

  8. R. E. Bryant, Y. A. Chen, “Verification of arithmetic circuits with binary moment diagrams”, Proc. 32th ACM/IEEE Design Automation Conference, (San Francisco, CA), pp. 535–541, 1995.

    Google Scholar 

  9. J. R. Burch, E. M. Clark, D. E. Long, “Symbolic model checking with partitioned transition relations”, Proc. of Int. Conf. on VLSI, 1991.

    Google Scholar 

  10. E. M. Clare, K. L. McMillen, X. Zhao, M. Fujita, J. C.-Y. Yang, “Spectral transforms for large Boolean functions with application to technology mapping”, Proc. 30th ACM/IEEE Design Automation Conference (Dallas, TX), pp. 54–60, 1993.

    Google Scholar 

  11. O. Coudert, C. Berthet, J. C. Madre, “Verification of synchronous sequential machines using symbolic execution”, Proc. Workshop on Automatic Verification Methods for Finite State Machines, Lecture Notes in Computer Science vol. 407, pp. 365–373, 1989.

    Google Scholar 

  12. O. Coudert, J. C. Madre, “A unified framework for the formal verification of sequential circuits”, Proc. IEEE International Conference on Computer-Aided Design, pp. 126–129, 1990.

    Google Scholar 

  13. O. Coudert, J. C. Madre, “The implicit set paradigm: A new approach to finite state system verification”, Formal Methods in System Design, No. 6(2), pp. 133–145, 1995.

    Article  Google Scholar 

  14. R. Drechsler, W. Günther, “Using lower bounds during dynamic BDD minimization”, Proc. of IEEE International Conference on Computer-Aided Design, pp. 29–32, 1999.

    Google Scholar 

  15. R. Drechsler, A. Sarabi, M. Theobald, B. Becker, M. A. Perkowski, “Efficient representation and manipulation of switching functions based on ordered Kronecker functional decision diagrams”, Proc. 31st ACM/IEEE Design Automation Conference, (San Diego, CA), pp. 415–419, 1994.

    Google Scholar 

  16. E. Dubrova, H. Sack, “Probabilistic verification of multiple-valued functions”, Proc. of the 30th Int. Symp. on Multiple Valued Logic (ISMVL 2000), 2000.

    Google Scholar 

  17. S. J. Friedman, K. J. Supowit, “Finding the optimal variable ordering for binary decision diagrams”, IEEE Transactions on Computers, No. 39, pp. 710–713, 1990.

    Article  MathSciNet  Google Scholar 

  18. M. Fujita, H. Fujisawa, N. Kawato, “Evaluation and improvements of Boolean comparison method based on binary decision diagrams”, Proc. of International Conference on Computer-Aided Design (Santa Clara, CA), pp. 2–5, 1988.

    Google Scholar 

  19. M. Fujita, Y. Matsunaga, K. Kakuda, “On variable ordering of binary decision diagrams”, Proc. of European Design Automation Conference EDAC, 1991.

    Google Scholar 

  20. M. R. Garey, D. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman, 1978.

    Google Scholar 

  21. D. Geist, I. Beer, “Efficient model checking by automated ordering of transition relation partitions”, Proc. Computer-Aided Verification, vol. 818, pp. 299–310, 1994.

    Article  Google Scholar 

  22. J. Gergov, Ch. Meinel, “Frontiers of feasible and probabilistic feasible Boolean manipulation with branching programs”, Symposium on Theoretical Aspects in Computer Science, Springer-Verlag, volume 665 of Lecture Notes in Computer Science, pp. 576–585,1993.

    Google Scholar 

  23. J. Gergov, Ch. Meinel, “MOD-2-OBDDs — a data structure that generalizes EXOR-sum-of-products and ordered binary decision diagrams”, Formal Methods in System Design, No. 8, pp. 273–282, 1996.

    Article  Google Scholar 

  24. H. Higuchi, F. Somenzi, “Lazy group sifting for efficient symbolic state traversal of FSMs”, Proc. of IEEE International Conference on Computer-Aided Design, 1999.

    Google Scholar 

  25. J. Jain, W. Adams, M. Fujita, “Sampling schemes for computing OBDD variable orderings”, Proc. IEEE International Conference on Computer-Aided Design, pp. 331–638, 1998.

    Google Scholar 

  26. J. Jain, J. Bitner, D. S. Fussell, J. A. Abraham, “Probabilistic verification of Boolean functions”, Proc. Formal Methods in System Design 1, Kluwer Academic Publishers, pp. 65–116, 1992.

    Google Scholar 

  27. U. Kebschull, E. Schubert, W. Rosenstiel, “Multilevel logic synthesis based on functional decision diagrams”, Proc. European Design Automation Conference, pp. 43–47, 1992.

    Google Scholar 

  28. Y. T. Lai, M. Pedram, S. B. K. Vrudhula, “EVBDD-based algorithms for integer linear programming, spectral transformation and function decomposition”, IEEE Trans. on Computer-Aided Design, Vol. 13, pp. 959–975, 1994.

    Article  Google Scholar 

  29. S. Lawrence, C. L. Gilles, “Accessibility of information on the web”, Nature, Volume 400, Number 6740, 1999.

    Google Scholar 

  30. S. Malik, A. Wang, R. K. Brayton, A. Sangiovanni-Vincentelli, “Logic verification using binary decision diagrams in a logic synthesis environment”, Proc. IEEE International Conference on Computer-Aided Design, (Santa Clara, CA), pp. 6–9, 1988.

    Google Scholar 

  31. K. L. McMillan, Symbolic Model Checking, Kluwer Academic Publishers, 1993.

    Google Scholar 

  32. Ch. Meinel, “Modified Branching Programs and Their Computational Power”, Springer-Verlag, Lecture Notes in Computer Science Vol. 370, 1998.

    Google Scholar 

  33. Ch. Meinel, A. Slobodová, “Speeding up variable reordering of OBDDs”, Proc. of the International Conference on Computer Design, pp. 338–343, 1997.

    Google Scholar 

  34. Ch. Meinel, F. Somenzi, T. Theobald, “Linear sifting of decision diagrams”, Proc. 34th ACM/IEEE Design Automation Conference (Anaheim, CA), pp. 202–207, 1997.

    Google Scholar 

  35. Ch. Meinel, T. Theobald, “Local encoding transformations for optimizing OBDD-representations of finite state machines”, Proc. International Conference on Formal Methods in Computer-Aided Design (Palo Alto, CA), volume 1166 of Lecture Notes in Computer Science, pp. 404–418. Springer, 1996.

    Google Scholar 

  36. Ch. Meinel, T. Theobald, Algorithms and Data Structures in VLSI-Design, Springer-Verlag, Berlin, New York, 1998.

    Book  MATH  Google Scholar 

  37. Ch. Meinel, H. Sack, “⊕-OBDDs — a BDD structure for probabilistic verification”, Proc. Workshop on Probabilistic Methods in Verification, pp. 141–151, 1998.

    Google Scholar 

  38. Ch. Meinel, H. Sack, “Algorithmic considerations for parity-OBDD reordering”, Proc. of the 1999 IEEE/ACM Int. Workshop on Logic Synthesis (IWLS99), pp. 71–74, 1999.

    Google Scholar 

  39. Ch. Meinel, K. Schwegmann, A. Slobodová, “Application driven variable reordering and an example implementation in reachability analysis”, Proc. of ASP-DAC′99, Hongkong, pp. 327–330, 1999.

    Google Scholar 

  40. Ch. Meinel, F. Somenzi, T. Theobald, “Linear sifting of decision diagrams”, Proc. of 34th IEEE International Conference on Computer-Aided Design, (Anaheim, CA), IEEE Computer Society Press, pp. 202–207, 1997.

    Google Scholar 

  41. Ch. Meinel, F. Somenzi, T. Theobald, “Function decomposition and synthesis using linear sifting”, Proc. ASP-DAC′98, (Yokohama, Japan), pp. 81–86, 1998.

    Google Scholar 

  42. Ch. Meinel, Ch. Stangier, “Speeding up symbolic model checking by accelerating dynamic variable reordering”, Proc. of 10th ACM Great Lake Symposium on VLSI, (Chicago, USA), pp. 39–42, 2000.

    Google Scholar 

  43. Ch. Meinel, A. Wagner, “WWW.BDD-Portal.Org — an electronic basis for cooperative research in EDA”, Proc. CRIS 2000, (Espoo, Finnland), pp. 1–7, 2000.

    Google Scholar 

  44. S. Minato, “Zero-suppressed BDDs for set manipulation in combinatorial problems”, Proc. 30th ACM/IEEE Design Automation Conference, (Dallas, TX), pp. 272–277, 1993.

    Google Scholar 

  45. S. Minato, N. Ishiura, S. Yajima, “Shared binary decision diagrams with attributed edges”, Proc. 27th ACM/IEEE Design Automation Conference (Florida, FL), pp. 52–57, 1990.

    Google Scholar 

  46. R. Rudell, “Dynamic variable ordering for ordered binary decision diagrams”, Proc. IEEE International Conference on Computer-Aided Design, (Santa Clara, CA), pp. 42–47, 1993.

    Google Scholar 

  47. H. Sack, E. Dubrova, Ch. Meinel, “Mod-p decision diagrams: A data-structure for multiple-valued functions”, Proc. of the 2000 IEEE/ACM Int. Workshop on Logic Synthesis IWLS, pp. 341–348, 2000.

    Google Scholar 

  48. D. Sieling, “On the existence of polynomial time approximation schemes for OBDD Minimization”, Proc. of Symposium on theoretical aspects in Computer Science, pp. 205–215, 1998.

    Google Scholar 

  49. A. Slobodová, Ch. Meinel, “Sample method for minimization of OBDDs”, Proc. of the International Workshop on Logic Synthesis, pp. 311–316, 1998.

    Google Scholar 

  50. S. Tani, K. Hamaguchi, S. Yajima, “The complexity of the optimal variable ordering problems of shared binary decision diagrams”, Proc. International Symposium on Algorithms and Computation ′93, Springer-Verlag, Lecture Notes in Computer Science 762, pp. 389–398, 1993.

    Google Scholar 

  51. S. Waack, “On the descriptive and algorithmic power of parity ordered binary decision diagrams”, Proc. 14th Symp. on Theoretical Aspects of Computer Science, Springer-Verlag, LNCS 1200, pp. 201–212, 1997.

    Google Scholar 

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Authors
  1. Randal E. Bryant
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  2. Christoph Meinel
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Editor information

Editors and Affiliations

  1. Tufts University, USA

    Soha Hassoun

  2. Kyushu Institute of Technology, Japan

    Tsutomu Sasao

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Bryant, R.E., Meinel, C. (2002). Ordered Binary Decision Diagrams. In: Hassoun, S., Sasao, T. (eds) Logic Synthesis and Verification. The Springer International Series in Engineering and Computer Science, vol 654. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0817-5_11

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  • DOI: https://doi.org/10.1007/978-1-4615-0817-5_11

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-5253-2

  • Online ISBN: 978-1-4615-0817-5

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