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Logic Synthesis and Verification

  • Soha Hassoun
  • Tsutomu Sasao

Table of contents

  1. Front Matter
    Pages iii-xv
  2. Olivier Coudert, Tsutomu Sasao
    Pages 1-27
  3. Masahiro Fujita, Yusuke Matsunaga, Maciej Ciesielski
    Pages 29-63
  4. Ellen Sentovich, Daniel Brand
    Pages 65-88
  5. Leon Stok, Vivek Tiwari
    Pages 115-139
  6. Rajeev Murgai
    Pages 141-165
  7. Olivier Coudert
    Pages 167-196
  8. Luca Benini, Giovanni De Micheli
    Pages 197-223
  9. Soha Hassoun, Tiziano Villa
    Pages 225-253
  10. Luciano Lavagno, Steven M. Nowick
    Pages 255-284
  11. Randal E. Bryant, Christoph Meinel
    Pages 285-307
  12. Wolfgang Kunz, João Marques-Silva, Sharad Malik
    Pages 309-341
  13. Andreas Kuehlmann, Cornelis A. J. van Eijk
    Pages 343-372
  14. Yuji Kukimoto, Michel Berkelaar, Karem Sakallah
    Pages 373-401
  15. Robert K. Brayton
    Pages 403-434
  16. Back Matter
    Pages 435-454

About this book

Introduction

Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this maturity is assuring, the advances in fabrication continue to seemingly present unwieldy challenges.
Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification. It consists of fifteen chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references.
Two unique features of this book are technical strength and comprehensiveness. The book chapters are written by twenty-eight recognized leaders in the field and reviewed by equally qualified experts. The topics collectively span the field.
Logic Synthesis and Verification fills a current gap in the existing CAD literature. Each chapter contains essential information to study a topic at a great depth, and to understand further developments in the field. The book is intended for seniors, graduate students, researchers, and developers of related Computer-Aided Design (CAD) tools.
From the foreword: "The commercial success of logic synthesis and verification is due in large part to the ideas of many of the authors of this book. Their innovative work contributed to design automation tools that permanently changed the course of electronic design." by Aart J. de Geus, Chairman and CEO, Synopsys, Inc.

Keywords

Analysis CAD algorithms automation computer computer-aided design (CAD) integrated circuit logic optimization verification

Editors and affiliations

  • Soha Hassoun
    • 1
  • Tsutomu Sasao
    • 2
  1. 1.Tufts UniversityUSA
  2. 2.Kyushu Institute of TechnologyJapan

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4615-0817-5
  • Copyright Information Kluwer Academic Publishers 2002
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4613-5253-2
  • Online ISBN 978-1-4615-0817-5
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site