Skip to main content
Log in

The implicit set paradigm: A new approach to finite state system verification

  • Published:
Formal Methods in System Design Aims and scope Submit manuscript

Abstract

This paper presents a new state of the art in the field of finite state system verification. The paradigm of this approach is to represent and to manipulate these systems in an implicit, way. The computational costs of the verification procedures using this paradigm depend on the costs of the operations performed on this implicit representation instead of the number of states and transitions of the verified systems. This paradigm allows these new verification procedures to overcome the limitations of previously availble techniques.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. S.B. Akers, “Binary Decision Diagrams,”IEEE Transactions on Computers, Vol. C-27, No. 6, 1978.

  2. P. Ashar, A. Ghosh, S. Devadas, and A.R. Newton, “Combinational and Sequential Logic Verification Using General Binary Decision Diagrams,” inProc. of International Workshop on Logic Synthesis, MCNC North Carolina, May 1991.

  3. C.L. Berman, “Ordered Binary Decision Diagrams and Circuit Structure,” inProc. of International Conference on Computer Design'89, Cambridge, Massachusetts, September 1989.

  4. G. Berry “A Hardware Implementation of ESTEREL,” inProc. of 1991 International Workshop on Formal Methods in VLSI Design, Miami Florida, January 1991.

  5. G. Berry, “ESTEREL on Hardware,” inProc. of the Royal Society Discussion Meeting on Mechanized Reasoning and Hardware Design, London, UK, October 1991.

  6. G. Berry et al., “The ESTEREL language,” inIEEE Special Issue on Synchronous Languages, September 1992.

  7. C. Berthet O. Coudert, and J.C. Madre, “New Ideas on Symbolic Manipulations of Finite State Machines,” inProc. of International Conference on Computer Design'90, Cambridge, Massachusetts, September 1990.

  8. J.P. Billon, “Symbolic Execution of Discrete Programs,” BULL Research Report No. 87039, September 1987.

  9. S. Bose and A. Fisher, “Automatic Verification of Synchronous, Circuits Using Symbolic Logic Simulation and Temporal Logic,” inFormal VLSI Correctness Verification, L.J.M. Claesen Editor, North-Holland, pp. 151–158, November 1989.

  10. A. Bouali and R. de Simone, “Symbolic Bisimulation Minimisation,” submitted toComputer Aided Verification Workshop'92, Montreal, Canada, 1992.

  11. K.S. Brace, R.L. Rudell, and R.E. Bryant, “Efficient Implementation of a BDD Package,” inProc, of 27th Design Automation Conference, Orlando, Florida, June 1990.

  12. R.E. Bryant, “Graph-Based Algorithms for Boolean Functions Manipulation,”IEEE Transactions on Computers, Vol. C35, No. 8, pp. 677–692, August 1986.

    Google Scholar 

  13. R.E. Bryant, “On the complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication,” Carnegie, Mellon University Research Report, September 1988.

  14. R.E. Bryant, D.L. Beatty, and C.-J.H. Seger, “Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation,” inProc. of 28th Design Automation Conference, pp. 397–402, San Francisco, California, June 1991.

  15. S. Burch, E.M. Clarke, K.L. McMillan, D.L. Dill, and L.J. Hwang., ‘Symbolic Model Checking: 1020 States and Beyond,” inProc. of Logic In Computer Science, Philadelphia, June 1990.

  16. S. Burch, E.M. Clarke, and K.L. McMillan, “Sequential Circuit Verfication Using Symbolic Model Checking,” inProc. of 28th Design Automation Conference, Orlando, Florida, July 1990.

  17. S. Burch, E.M. Clarke, and D.E. Long, “Representing Circuits More Efficiently in Symbolic Model Checking,” inProc. of 28th Design Automation Conference, pp. 403–407, San Francisco, California June 1991.

  18. K.M. Butler, D.E. Ross, R. Kapur, and M.R. Mercer, “Heuristics to Compute Variable Orderings for Efficient Manipulations of Ordered Binary Decision Diagrams,” inProc. of 28th Design Automation Conference, pp. 417–420, San Francisco, California June 1991.

  19. N. Calazans, R. Jacobi, Q. Zhang, and C. Trullemans, “Improving BDD manipulation through Incremental Reduction and Enhanced Heuristics,” inProc. of CICC'91, May 1991.

  20. H. Cho, G.D. Hachtel, S.W. Jeong, B. Plessier, E. Schwarz, and F. Somenzi, “ATPG Aspect of FSM Verification,” inProc. of IEEE international Conference on Computer Aided Design'90, Santa Clara, California, November 1990.

  21. E.M. Clarke, E.A. Emerson, and A.P. Sistla, “Automatic Verification of Finite-State Concurrent Systems Using Temporal Logic Verification,” in ACM Trans. Programming Language System, Vol. 8, No. 2, 1986.

  22. E.M. Clarke and O. Grumbreg, “Research on Automatic Verification, of Finite-State Concurrent Systems,”Annual Revue Computing Science, Vol. 2, pp. 269–290, 1987.

    Google Scholar 

  23. D.R. Coelho,The VHDL Handbook, Kluwer Academic Publishers, 1989.

  24. O. Coudert, C. Berthet, and J.C. Madre, “Verification of Synchronous Sequential Machines Based on Symbolic Execution,” inLecture Notes in Computer Science: Automatic Verification Methods for Finite State Systems, Vol. 407, J. Sifakis Editor, Springer-Verlag, pp. 365–373., June 1989.

  25. O. Coudert, C. Berthet, and J.C. Madre, “Verification of Sequential Machines using Boolean Functional Vectors,” inFormal VLSI Correctness Verification, L.J.M. Claesen Editor, North-Holland, pp. 179–196, November 1989.

  26. O. Coudert and J.C. Madre, “Verifying Temporal Properties of Sequential Machines Without, Building their State Diagrams,” inComputer-Aided Verification'90, E.M. Clarke and R.P. Kurshan Editors, DIMACS, Series, pp. 75–84, June 1990.

  27. O. Coudert and C. Madre, “A Unified Framework for the Formal Verification, of Sequential Circuits,” inProc. of IEEE International Conference on Computer Aided Design'90, Santa, Clara, California, November 1990.

  28. O. Coudert,SIAM: Une Boite à Outils pour la Preuve Formelle de Systèmes Séquentiels, Ph.D. Thesis, Ecole National Supérieure des Télécommunications, Paris, France, October 1991.

    Google Scholar 

  29. A. Debreil, C. Berthet, and A. Jerraya, “Symbolic Computation of VHDL Hierarchial Descriptions,” inProc. of the First European Conference on VHDL Methods, Marseilles, France, September, 1990.

  30. S. Devadas, H.K. Ma, and R. Newton, “On the Verification of Sequential Machines at Differing Levels of Abstraction,”IEEE Transactions on CAD, Vol. 7, No. 6, June 1988.

  31. E.A. Emerson, “Temporal and Modal Logic,”Formal Models and Semantics, Handbook of Theorical Computer Science, Jan van Leeuwen Editor, Elsevier, pp. 995–1072, 1990.

  32. R. Enders, T. Filkorn and D. Taubner, “Generating BDDs for Symbolic Model Checking in CCS”, inProc. of the Computer Aided Verification Workshop'91, Aalborg, Denmark, 1991.

  33. S.J. Friedman, and K.J. Supowit, “Finding the Optimal Variable Ordering for Binary Decision Diagrams,”IEEE Transactions on Computer, Vol. C-39., No. 5, pp. 710–713, May 1990.

    Google Scholar 

  34. M. Fujita, H. Fujisawa, and N. Kawato, “Evaluation and Improvements of Boolean Comparison Methods Based Binary Decision Diagrams”Proc. of IEEE International Conference on Computer Aided Design'88, Santa Clara, California, November 1988.

  35. A. Ghosh and S. Devadas, “A Mixed Depth-First/Breadth-First Traversal Technique for Sequential Verification,” inProc. of the International Workshop on Logic Synthesis, MCNC, North Carolina, May 1991.

  36. N. Halbwachs, P. Caspi, P. Raymond, and D. Pilaud, “The Synchronous Data-Flow Programming Language LUSTRE,” inIEEE Special Issue on Synchronous Languages, pp. 1305–1320, September 1992.

  37. H. Hiraishi, K. Hamaguchi, H. Ochi, and S. Yajima, “Vectorized Symbolic Model Checking of Computational Tree Logic for Sequential machine Verification,” inProc. of the Computer Aided Verification Workshop'91, Aalborg, Denmark, 1991.

  38. G.J. Holtman, “Algorithms for Automated Protocol Validation,” inProc. of the Workshop on Automatic Verification Methods for Finite State Systems, Grenoble, France, June 1989.

  39. J.E. Hopcroft and J.D. Ullman,Introduction to Automata Theory, Languages and Computation, Addison-Wesley, Reading, Massachusetts, 1979.

    Google Scholar 

  40. S.H. Hwang and A.R. Newton, “An efficient Design Correctness Checker of Finite State Machines,” inProc. of IEEE International Conference on Computer Aided Design'87, Santa Clara, California, November 1987.

  41. N. Ishiura, H. Sawada, and S. Yajima, “Minimization of Binary Decision Diagrams Based on Exchanges of Variables,” inProc. of IEEE International Conference on Computer Aided Design'91, Santa Clara, California, November 1991.

  42. R. Jacobi, N. Calazans, and C. Trullemans, “Incremental Reduction of Binary Decision Diagrams,” inProc. of ISCAS'91, June 1991.

  43. S.W. Jeong, B. Plessier, G.D. Hachtel, and F. Somenzi, “Variable Ordering for FSM Traversal,” inProc. of the International Workshop on Logic Synthesis, MCNC, North Carolina, May 1991.

  44. S.C. Kleene,Mathematical Logic, John Wiley and Sons, NY, 1967.

    Google Scholar 

  45. B. Lin, H.J. Touati, and A.R. Newton, “Don't Care Minimization of Multi-Level Sequential Logic Networks,” inProc. of IEEE International Conference on Computer Aided Design'90, Santa Clara, California, November 1990.

  46. B. Lin, “Efficient Symbolic Manipulation of Equivalence Relations and Classes,” inProc. of the International Workshop on Logic Synthesis, MCNC, North Carolina, May 1991.

  47. K.L. McMillan and J.C. Schwalbe, “Formal Verification of the Encore Gigamax Cache Consistency Protocol,” inProc, of the International Symposium on Shared Memory Multiprocessors, 1991.

  48. J.C. Madre and J.P. Billon, “Proving Circuit Correctness using Formal Comparison Between Expected and Extracted Behaviour,” inProc. of the 25th Design Automation Conference, Anaheim, California, July 1988.

  49. J.C. Madre, “PRIAM, Un Outil de Preuve Formelle de Circuits Digitaux,” Thèse de troisième cycle, Ecole Nationale Supérieure des Télécommunications, Paris, France, June 1990.

    Google Scholar 

  50. S. Malik, A.R. Wang, R.K. Brayton and A. Sangiovanni-Vincentelli, “Logic Verification using Binary Decision Diagrams in a Logic Synthesis Environment,” inProc. of IEEE International Conference on Computer Aided Design'88, Santa Clara, California, pp. 6–9, November 1988.

  51. S. Minato, N. Ishiura, and S. Yajima, “Fast Tautology Checking Using Shared Binary Decision Diagrams-Experimental Results,” inFormal VLSI Correctness Verification, L.J.M. Claesen Editor, North-Holland, pp. 107–111, November 1989.

  52. S. Minato, N. Ishiura, and S. Yajima, “Shared Binary Decision Diagrams with Attributed Edges for Efficient Boolean Function Manipulation,” inProc. of the 27th Disign Automation Conference, Las Vegas, Nevada, pp. 52–57, June 1990.

  53. C. Pixley, “A Computational Theory and Implementation of Sequential Hardware Equivalence,” inProc. of the Computer Aided Verification'90, E.M. Clarke and R.P. Kurshan Editors, DIMACS Series, pp. 293–320, June 1990.

  54. C. Pixley, S.W. Jeong, and G.D. Hachtel, “Exact Calculation of Synchronization sequences Based on Binary Decision Diagrams,” inProc. of 29th Design Automation Conference, Anaheim, California, 1992.

  55. J.P. Quielle and J. Sifakis, “Fairness and Related Properties in Transition Systems,”Acta Informatica, pp. 195–220, 1983.

  56. C. Ratel, N. Halbwachs, and P. Raymond, “Programming and verifying Critical Systems by Means of the Synchronous Dataflow Programming Language LUSTRE,” inProc. of ACM SigSoft Conference on Software for Critical Systems, New Orleans, December 1991.

  57. K.J. Supowit and S.J. Friedman, “A new Method for Verifying Sequential Circuits,” inProc. of the 23rd Design Automation Conference, 1986.

  58. G. Thuau and B. Berkane, “Using the Language LUSTRE for Sequential Circuit Verification,” inProc. of the International Workshop on Designing Correct Circuits, Lingby, Denmark, January 1992.

  59. H.J. Touati, H. Savoj, B. Lin, R.K. Brayton, and A. Sangiovanni-Vincentelli, “Implicit State Enumeration of Finite State Machines using BDD's,” inProc. of IEEE International Conference on Computer Aided Design'90, Santa Clara, California, November 1990.

  60. H.J. Touati, R.K. Brayton, and R. Kurshan, “Testing Language Containment for ω Automata using BDD's,” inProc. of the 1991 International Workshop on Formal Methods in VLSI Design, Miami, Florida, January 1991.

  61. F. Van Aelten, J. Allen, and S. Devadas, “Verification of Relations between Synchronous Machines,” inProc. of IEEE International Conference on Computer Aided Design'91, Santa Clara, California, November 1991.

  62. S. Yang,Logic Synthesis and Optimization Benchmarks User Guide, Microelectronics Center of North Carolina, January 1991.

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

About this article

Cite this article

Coudert, O., Madre, J.C. The implicit set paradigm: A new approach to finite state system verification. Form Method Syst Des 6, 133–145 (1995). https://doi.org/10.1007/BF01383965

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF01383965

Keywords

Navigation