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An error-tolerant serial binary full-adder via a spiking neural P system using HP/LP basic neurons

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Abstract

We present an implementation of an improved adder via a spiking neural P system. Our adder processes arbitrary length binary numbers, and thus, is suitable for cryptographic applications. Due to the use of dual-rail logic, the adder is also error tolerant. We present the implementation concept, as well as a simulation model in System-C.

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Acknowledgements

This work has been supported by the Mongolian Foundation for Science and Technology (Research Grants ShUSS-2018/04 and MOST-MECSS2017001), and the School of Information and Communication Technology, MUST (Research Grant SICT201801). This work has been presented at the 20th Conference on Membrane Computing in Curtea de Arges, Romania, August 5–8, 2019.

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Authors and Affiliations

  1. Department of Information and Computer Sciences, School of Engineering and Applied Sciences, National University of Mongolia, Ulaanbaatar, Mongolia

    Otgonnaran Ochirbat

  2. Department of Computer Science School of Information and Communication Technology, Mongolian University of Science and Technology, Ulaanbaatar, Mongolia

    Tseren-Onolt Ishdorj & Gordon Cichon

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  1. Otgonnaran Ochirbat
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  2. Tseren-Onolt Ishdorj
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  3. Gordon Cichon
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Correspondence to Gordon Cichon.

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Ochirbat, O., Ishdorj, TO. & Cichon, G. An error-tolerant serial binary full-adder via a spiking neural P system using HP/LP basic neurons. J Membr Comput 2, 42–48 (2020). https://doi.org/10.1007/s41965-020-00033-3

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  • DOI: https://doi.org/10.1007/s41965-020-00033-3

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