Power Optimized Domino Logic Design of a Comparator with Variable Threshold CMOS and Clock Gating

Abstract

This paper’s objective is to design and analyze the comparator circuit employing domino logic with Variable Threshold Complementary Metal Oxide Semiconductor (VTCMOS) and extra clock gating hardware. VTCMOS is a useful technique for reducing static power consumption, since it uses low supply voltage and small threshold voltage while retaining high speed. Clock gating is employed to reduce dynamic power consumption. A multiplexer is utilized for the sake of clock gating and to maintain the state of a circuit constant. When the circuit is in active mode, the clock signal is transmitted through the domino logic, and when the circuit is in standby mode, the clock signal is bypassed to retain the circuit in the same condition. In comparison to static CMOS logic, the domino logic technique reduces the area while increasing speed. In 90 nm CMOS technology, a two input, three output 1-bit comparator is built. The assessed metrics include static power when no input transition occurs, dynamic power when an input transition occurs, and delay and power delay product (PDP). When comparing traditional domino logic, FDST domino logic, and GCRK domino logic with suggested domino logic, and simulation results are also included.