Abstract
Domino logic is widely used for high switching speed and high-performance circuits. Domino logic consists of an inverter used between two stages of dynamic logic. Robustness of domino logic degrades with scaling down as leakage power increases. This paper presents a new proposed domino logic circuit with improved speed. Present work proposed domino logic scheme which gives static output also in evaluation phase with high frequency inputs. Conventional domino styles do not provide static output with changing inputs during evaluation phase. This proposed circuit is designed by making use of current mirror circuit and modified keeper circuitry. The proposed circuit has low power-delay product as compared to conventional domino logic styles. All the circuits have been simulated in cadence virtuoso 180 nm technology. According to simulation results obtained, the circuit shows more than 50 % better performance as compared to conventional domino styles.
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Sharma, S., Kashyap, K.K. (2015). A Novel Low-Power Domino Logic Technique Providing Static Output in Evaluation Phase for High Frequency Changing Inputs. In: Jain, L., Patnaik, S., Ichalkaranje, N. (eds) Intelligent Computing, Communication and Devices. Advances in Intelligent Systems and Computing, vol 308. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2012-1_47
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DOI: https://doi.org/10.1007/978-81-322-2012-1_47
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