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Modifications in CMOS Dynamic Logic Style: A Review Paper

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Abstract

Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper, an overview and classification of these techniques are first presented and then compared according to their performance.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology Rourkela, Sector-1, Rourkela, 769008, Orissa, India

    Preetisudha Meher & Kamalakanta Mahapatra

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  1. Preetisudha Meher
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  2. Kamalakanta Mahapatra
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Correspondence to Preetisudha Meher.

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Meher, P., Mahapatra, K. Modifications in CMOS Dynamic Logic Style: A Review Paper. J. Inst. Eng. India Ser. B 96, 391–399 (2015). https://doi.org/10.1007/s40031-014-0150-8

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  • DOI: https://doi.org/10.1007/s40031-014-0150-8

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