Abstract
In this paper, we propose a technique for lowering the latency of the communication in a NoC (network on chip). The technique, which can support two qualities of service (QoS), i.e., the guaranteed throughput (GT) and best effort (BE), is based on splitting a wider link into narrower links to increase throughput and decrease latency in the NoC. In addition, to ease the synchronization and reduce the crosstalk, we use the 1-of-4 encoding for the smaller buses. The use of the encoding in the proposed NoC architecture considerably lowers the latency for both BE and GT packets. In addition, the bandwidth is increased while the power consumption of the links is reduced.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Benini, L., de Micheli, G., 2002. Network on chips: a new SoC paradigm. IEEE Computer, 35(1):70–78. [doi:10.1109/2.976921]
Bertozzi, D., Benini, L., 2004. Xpipes: a network-on-chip architecture for gigascale systems-on-chip. IEEE Circuts Syst. Mag., 4(2):18–31. [doi:10.1109/MCAS.2004.1330747]
Davis, J., Meindl, D., 2000. Compact distributed RLC interconnect models—Part II: coupled line transient expressions and peak crosstalk in multilevel networks. IEEE Trans. on Electr. Dev., 47(11):2078–2087. [doi:10.1109/16.877169]
Im, S., Srivastava, N., Banerjee, K., Goodson, K.E., 2005. Scaling analysis of multilevel interconnect temperatures for high-performance ICs. IEEE Trans. on Electr. Dev., 52(12):2710–2719. [doi:10.1109/TED.2005.859612]
Kim, M., Kim, D., Sobelman, G.E., 2006. Network-on-Chip Link Analysis under Power and Performance Constraints. Proc. Design Automation and Test in Europe Conf. and Exhibition, Island of Kos, Greece, p.4163–4166. [doi:10.1109/ISCAS.2006.1693546]
Millberg, M., Nilsson, E., Thid, R., Jantsch, A., 2004. Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip. Proc. Conf. on Design, Automation and Test in Europe, Paris, France, p.890–895. [doi:10.1109/DATE.2004.1269001]
Nigussie, E., Lehtonen, T., Tuuna, S., Plosila, J., Isoaho, J., 2007. High-performance long NoC link using delay-insensitive current-mode signaling. VLSI Design, p.1–13. [doi:10.1155/2007/46514]
Rijpkema, E., Goossens, K., Radulescu, A., Dielissen, J., Meerbergen, J.V., Wielage, P., Waterlander, E., 2003. Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip. IEE Proc.-Comput. Digit. Tech., 150(5):294–302. [doi:10.1049/ip-cdt:20030830]
Saneei, M., Afzali-Kusha, A., Navabi, Z., 2006. A Mesochronous Technique for Communication in Network on Chips. Proc. 18th Int. Conf. on Microelectronics, Saudi Arabia, p.32–35. [doi:10.1109/ICM.2006.373260]
Santi, S., Lin, B., Kocarev, L., Maggio, G.M., Rovatti, R., Setti, G., 2005. On the Impact of Traffic Statistics on Quality of Service for Networks on Chip. IEEE Int. Symp. on Circuits and Systems, Kobe, Japan, p.2349–2352. [doi:10.1109/ISCAS.2005.1465096]
Vellanki, P., Banerjee, N., Chatha, K.S., 2005. Quality-of-service and error control techniques for mesh-based network-on-chip architectures. Integr., VLSI J., 38(3):353–382. [doi:10.1016/j.vlsi.2004.07.009]
Verhoeff, T., 1988. Delay-insensitive codes—an overview. Distrib. Comput., 3(1):1–8. [doi:10.1007/BF01788562]
Author information
Authors and Affiliations
Corresponding author
Additional information
Project supported by the Iranian National Science Foundation
Rights and permissions
About this article
Cite this article
Saneei, M., Afzali-Kusha, A. & Navabi, Z. A low-power high-throughput link splitting router for NoCs. J. Zhejiang Univ. Sci. A 9, 1708–1714 (2008). https://doi.org/10.1631/jzus.A0720117
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1631/jzus.A0720117