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Directed block copolymer self-assembly for nanoelectronics fabrication

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Abstract

This paper provides an overview of directed self-assembly (DSA) options that exhibit potential for enabling extensible high-volume patterning of nanoelectronics devices. It describes the current set of research requirements, which a DSA technology must satisfy to warrant insertion consideration, and summarizes the state-of-the art. The primary focus is on chemical patterning and graphoepitaxial approaches to directing block copolymer (BCP) based assembly. These options exhibit the nearest-term potential, among the emerging DSA technologies, for satisfying projected International Technology Roadmap for Semiconductors (ITRS) patterning requirements. The paper concludes with a selected set of additional challenges, which represent potential barriers to the integration of directed BCP patterning into a nanoelectronics manufacturing line, as well as a few emerging application opportunities for related functional materials. A glossary of acronyms and terms may be found at the end of this manuscript.

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ACKNOWLEDGMENTS

Many people have contributed to moving directed self-assembly technology forward as a potential patterning option. Special thanks go to Drs. Michael Garner, Harry Levinson, Lloyd Litt, William Hinsberg, and Wayne Cascio for their thoughtful recommendations and contributions. The author also thanks those teams who continue to provide the needed theory, modeling, verification, and ongoing assessment. This includes colleagues within SRC, its member companies, and its academic research community; the ITRS Emerging Research Materials, Lithography, and Metrology Working Groups; and many others who helped to lay the foundations for understanding these networks of material systems.

Unless otherwise noted, the following definitions may be found in the Semiconductor Glossary, at Ref. 247:

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    Daniel J.C. Herr

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Correspondence to Daniel J.C. Herr.

Glossary of Acronyms and GlossaryTerms

Critical dimension (CD)

Dimensions of the smallest geometrical features (width of interconnect line, contacts, trenches, etc.) that can be formed during semiconductor device/circuit manufacturing using given technology.

Design rules

Specifications for the minimum dimensions of devices and interconnects comprising an integrated circuit adopted during design stage, deGlossaryTermined by the capabilities of process technology available.

Complementary metal oxide semiconductor (CMOS)

A structure that consists of N-channel and P-channel MOS transistors. Due to very low power consumption and dissipation as well minimization of the current in “off” state CMOS is a very effective device configuration for implementation of digital functions. CMOS is a key device in state-of-the-art silicon microelectronics.

Double patterning (DP)

A class of patterning technologies developed for extending manufacturable lithographic processes for semiconductor-related applications, by enabling enhanced the feature density. It includes the following technology options, such as dual-tone photoresist, dual-tone development, self-aligned spacers, and double-exposure processes. This technology serves as a bridge to the 22 nm technology node.248

Dynamic random access memory (DRAM)

A memory cell in which digital information (data) is stored in volatile state; information stored is lost unless charge is refreshed periodically (in contrast static RAM, or SRAM); loses its data when the power supply is removed; key component of digital circuits; the most mass produced type of an integrated circuit.

Environment, Safety, & Health (ESH)

(i) understand (characterize) processes and materials during the development phase, (ii) use materials that are less hazardous or whose byproducts are less hazardous, (iii) design products and systems (equipment and facilities) that consume less raw material and resources, and (4) make the factory safe for employees249

The ITRS ESH team (ITWG)

identifies challenges when new wafer processing and assembly technologies move through research and development phases and toward manufacturing insertion. The four basic ESH roadmap strategies are to:

International Technology Roadmap for Semiconductors (ITRS)

This endeavor reflects a global consensus on a 15-year projection of the semiconductor industry’s future technology requirements. These future needs drive present-day strategies for worldwide research and development among manufacturers’ research facilities, universities, and national labs.250

International Technology Working Group (ITWG)

The ITRS organization includes sponsoring organizations, the executive committee, known as the International Roadmap Committee (IRC). Regional and international technology working groups (TWGs/ITWGs), and the management office at SEMATECH. The ITRS teams are recognized experts that volunteer their time to work in a technology group in their expertise area.251

Line edge roughness (LER)

Line-edge roughness is a GlossaryTerm commonly used to describe roughness of the edge of the exposed and developed photoresist; a departure of the edge of the photoresist pattern from the perfectly straight line; a critically important issue in sub-90 nm photolithography; very difficult to work around as it is inherent to the nature of the photoresist material morphology.

L o

This material metric corresponds to the length of the symmetric lamellar period of a phase-segregated block copolymer.

L s

This patterning metric corresponds to the length of the lithographically defined period for alternating lines and spaces.

Microprocessor unit fabricated on one chip (MPU)

This system contains the basic elements of a computer, including logic and control, which are needed to process data.

Node

In previous editions of the ITRS, the GlossaryTerm “technology node” (or “hpXX node”) was used in an attempt to provide a single, simple indicator of overall industry progress in integrated circuit (IC) feature scaling. It was specifically defined as the smallest half-pitch of contacted metal lines on any product. Historically, DRAM has been the product which, at a given time, exhibited the tightest contacted metal pitch and, thus, it “sets the pace” for the ITRS technology nodes. However, we are now in an era in which there are multiple significant drivers of scaling and believe that it would be misleading to continue with a single highlighted driver, including DRAM. Today, the DRAM M1 half-pitch is just one among several historical indicators of IC scaling.252

PS–b-PtbocST

Polystyrene–b-p-tert-butyloxycarbonyloxystyrene diblock copolymer.

PEO–PPO

Poly(ethylene oxide)–poly(propylene oxide) diblock copolymer.

PEO–b-PPO–b-PEO

Poly(ethylene oxide)–b-poly(propylene oxide)–b-poly(ethylene oxide) triblock copolymer.

Pitch

The linear dimension that corresponds to the center-to-center distance between features of an integrated circuit, such as interconnect lines.

Resolution

This GlossaryTerm reflects the precision of the lithographic pattern transfer process. The smaller the geometries that can be defined, the higher the process resolution. It is deGlossaryTermined by several factors related to the exposure tool, resist, and masks used.

Sensitivity

This GlossaryTerm corresponds to the exposure dose required to expose a photoresist. The sensitivity of a photoresist is measured by its quantum efficiency, or the number of chemical reactions per photon absorbed or electron collisions within the resist. For photon and electron based lithographic processes the units of sensitivity are mJ/cm2 or µC/cm2, respectively. A photoresist’s sensitivity to a particular energy source drives the resist’s imaging functionality. There is a relationship between the amount of energy deposited in a polymer film and the extent of chemical reaction that directly affects the sensitivity and resolution of an electron resist. Factors that affect this relationship are beam voltage, polymer density, substrate density, atomic number, and electron dose.253 Other factors that affect the photoresist sensitivity include polymer composition and dispersity, the photoactive compound or photoacid generator, and the specific chemistry that enables the differential solubility required for pattern formation.

Triangle of death

The “triangle of death” reflects the interdependence of a resist’s line edge roughness, sensitivity, and resolution, which are considered related in the sense that one can define any two GlossaryTerms with the third GlossaryTerm being fixed by the values selected for the initial two GlossaryTerms, such that LER2 × dose ˜ constant related to resolution.254

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Herr, D.J. Directed block copolymer self-assembly for nanoelectronics fabrication. Journal of Materials Research 26, 122–139 (2011). https://doi.org/10.1557/jmr.2010.74

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